Table of Contents
Advertisement
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T
state of a general register write cycle, input capture takes priority and the write to
3
the general register is not performed. See figure 9.44.
φ
Address bus
Internal write signal
Input capture signal
TCNT
GR
Figure 9.44 Contention between General Register Write and Input Capture
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
φ
f =
(N+1)
(f: counter frequency. φ: system clock frequency. N: value set in general register.)
General register write cycle
T
T
1
2
GR address
M
Rev. 4.00 Jan 26, 2006 page 391 of 938
Section 9 16-Bit Timer
T
3
M
REJ09B0276-0400
Advertisement
Table of Contents
