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6.2.2
Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
7
Bit
AST7
Initial value
1
Read/Write
R/W
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0
Description
0
Areas 7 to 0 are accessed in two states
1
Areas 7 to 0 are accessed in three states
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings. These
settings are therefore meaningless in the single-chip modes (modes 6 and 7).
When the corresponding area is designated as DRAM space by bits DRAS2 to DRAS0 in DRAM
control register A (DRCRA), the number of access states does not depend on the AST bit setting.
When an AST bit is cleared to 0, programmable wait insertion is not performed.
6.2.3
Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
On-chip memory and registers are accessed in a fixed number of states that does not depend on
WCRH/WCRL settings.
6
5
AST6
AST5
1
1
R/W
R/W
Bits selecting number of states for access to each area
4
3
AST4
AST3
1
1
R/W
R/W
Rev. 4.00 Jan 26, 2006 page 125 of 938
Section 6 Bus Controller
2
1
AST2
AST1
1
1
R/W
R/W
(Initial value)
REJ09B0276-0400
0
AST0
1
R/W
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