Register Settings - Renesas H8/3067 Series User Manual

Renesas 16-bit single-chip microcomputer

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Section 14 Smart Card Interface

the receiving device places the signal line in the high-impedance state again. The signal line is

pulled high again by a pull-up resistor.

5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data

frame. If it receives an error signal, however, it returns to step 2 and transmits the same data

Register Settings

Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or

1 must be set to the value shown. The setting of other bits is described in this section.

Table 14.3 Smart Card Interface Register Settings

Notes: — Unused bit.

1. Lower 20 bits of the address in advanced mode.

2. When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0.

Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card

interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the

direct convention type, or set to 1 if of the inverse convention type.

Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section

14.3.5, Clock.

Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 14.3.5, Clock, for

the method of calculating the value to be set.

Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial

communication functions. See section 13, Serial Communication Interface, for details. The CKE1

and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable clock

Rev. 4.00 Jan 26, 2006 page 554 of 938

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