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Section 6 Bus Controller
• Figure 6.32 shows typical interconnections when using two 16-Mbit DRAMs using a × 8-bit
organization, and the corresponding address map. The DRAMs used in this example are of the
11-bit row address × 10-bit column address type. The CS
output pin for areas 2 and 3. When the DRAM address space spans a number of contiguous
areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single CS
pin to be used as the common RAS output pin for a number of areas, and makes it possible to
directly connect large-capacity DRAM with address space that spans a maximum of four areas.
Any unused CS pins (in this example, the CS
H8/3067 Group chip
Figure 6.32 Interconnections and Address Map for 16-Mbit DRAMs with × × × × 8-Bit
Rev. 4.00 Jan 26, 2006 page 186 of 938
REJ09B0276-0400
pin) can be used as input/output ports.
3
CS
(RAS
)
2
2
PB
(UCAS)
4
PB
(LCAS)
5
RD (WE)
A
, A
-A
21
10
1
D
-D
15
8
D
-D
7
0
(a) Interconnections (example)
PB
4
(UCAS)
15
8
7
H'400000
Area 2
DRAM
H'5FFFFE
(No.1)
H'600000
Area 3
H'7FFFFE
H'800000
Area 4
Normal
H'9FFFFE
H'A00000
Normal
Area 5
H'BFFFFE
16-Mbyte mode
(b) Address map
Organization
pin is used as the common RAS
2
2-CAS 16-Mbit DRAM
11-bit row address x 10-bit column address
x8-bit organization
RAS
CAS
WE
No.1
A
-A
10
0
D
-D
7
0
OE
RAS
CAS
WE
No.2
A
-A
10
0
D
-D
7
0
OE
PB
5
(LCAS)
0
CS
(RAS
)
2
2
DRAM
(No.2)
CS
4
CS
5
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