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Appendix B Internal I/O Registers
RTMCSR—Refresh Timer Control/Status Register
Bit
Initial value
Read/Write
Compare match flag
Note: Only 0 can be written to clear the flag.
Rev. 4.00 Jan 26, 2006 page 810 of 938
REJ09B0276-0400
7
6
5
CMF
CMIE
CKS2
0
0
0
R/(W)*
R/W
R/W
Refresh counter clock select
CKS2
0
1
Compare match interrupt enable
0
The CMI interrupt requested by the CMF flag is disabled
1
The CMI interrupt requested by the CMF flag is enabled
0
[Clearing conditions]
• Cleared by a reset and in standby mode
• Cleared by reading CMF when CMF = 1, then writing 0 in CMF
[Setting condition]
1
When RTCNT = RTCOR
H'EE028
4
3
2
CKS1
CKS0
0
0
1
R/W
R/W
CKS0
CKS1
Count operation halted
0
0
φ/2 used as counter clock
1
φ/8 used as counter clock
1
0
φ/32 used as counter clock
1
φ/128 used as counter clock
0
0
φ/512 used as counter clock
1
φ/2048 used as counter clock
1
0
φ/4096 used as counter clock
1
DRAM interface
1
0
1
1
Description
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