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Appendix A Instruction Set
Table A.3
Number of States per Cycle
Execution State
(Cycle)
Instruction fetch
Branch address read S
Stack operation
Byte data access
Word data access
Internal operation
Legend
m: Number of wait states inserted into external device access
Rev. 4.00 Jan 26, 2006 page 772 of 938
REJ09B0276-0400
Access Conditions
On-Chip Sup-
porting Module
On-Chip
8-Bit
Memory
Bus
S
2
6
I
J
S
K
S
3
L
S
6
M
S
1
N
External Device
8-Bit Bus
16-Bit
2-State
3-State
Bus
Access
Access
3
4
6 + 2m
2
3 + m
4
6 + 2m
16-Bit Bus
2-State
3-State
Access
Access
2
3 + m
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