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Section 10 8-Bit Timers
10.2
Register Descriptions
10.2.1
Timer Counters (TCNT)
Bit
15
14
Initial value
0
0
Read/Write
R/W
R/W
Bit
15
14
Initial value
0
0
Read/Write
R/W
R/W
The timer counters (TCNT) are 8-bit readable/writable up-counters that increment on pulses
generated from an internal or external clock source. The clock source is selected by clock select
bits 2 to 0 (CKS2 to CKS0) in the timer control register (TCR). The CPU can always read or write
to the timer counters.
The TCNT0 and TCNT1 pair, and the TCNT2 and TCNT3 pair, can each be accessed as a 16-bit
register by word access.
TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1 and
0 (CCLR1 and CCLR0) in TCR select the method of clearing.
When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status
register (TCSR) is set to 1.
Each TCNT is initialized to H'00 by a reset and in standby mode.
Rev. 4.00 Jan 26, 2006 page 402 of 938
REJ09B0276-0400
TCNT0
13
12
11
10
0
0
0
0
R/W
R/W
R/W
R/W
R/W
TCNT2
13
12
11
10
0
0
0
0
R/W
R/W
R/W
R/W
R/W
9
8
7
6
5
0
0
0
0
0
R/W
R/W
R/W
R/W
9
8
7
6
5
0
0
0
0
0
R/W
R/W
R/W
R/W
TCNT1
4
3
2
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
TCNT3
4
3
2
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
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