Table of Contents
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6.10 Bus Arbiter........................................................................................................................ 203
6.10.1 Operation ............................................................................................................. 203
6.11 Register and Pin Input Timing .......................................................................................... 206
6.11.1 Register Write Timing ......................................................................................... 206
6.11.2 BREQ Pin Input Timing ...................................................................................... 207
7.1
Overview........................................................................................................................... 209
7.1.1
Features................................................................................................................ 209
7.1.2
Block Diagram ..................................................................................................... 210
7.1.3
Functional Overview............................................................................................ 211
7.1.4
Input/Output Pins ................................................................................................. 212
7.1.5
Register Configuration......................................................................................... 212
7.2
Register Descriptions (1) (Short Address Mode) .............................................................. 214
7.2.1
Memory Address Registers (MAR) ..................................................................... 214
7.2.2
I/O Address Registers (IOAR) ............................................................................. 215
7.2.3
Execute Transfer Count Registers (ETCR).......................................................... 215
7.2.4
Data Transfer Control Registers (DTCR) ............................................................ 217
7.3
Register Descriptions (2) (Full Address Mode) ................................................................ 220
7.3.1
Memory Address Registers (MAR) ..................................................................... 220
7.3.2
I/O Address Registers (IOAR) ............................................................................. 220
7.3.3
Execute Transfer Count Registers (ETCR).......................................................... 221
7.3.4
Data Transfer Control Registers (DTCR) ............................................................ 223
7.4
Operation .......................................................................................................................... 229
7.4.1
Overview.............................................................................................................. 229
7.4.2
I/O Mode.............................................................................................................. 231
7.4.3
Idle Mode............................................................................................................. 233
7.4.4
Repeat Mode ........................................................................................................ 236
7.4.5
Normal Mode....................................................................................................... 240
7.4.6
Block Transfer Mode ........................................................................................... 243
7.4.7
DMAC Activation................................................................................................ 248
7.4.8
DMAC Bus Cycle ................................................................................................ 250
7.4.9
Multiple-Channel Operation ................................................................................ 256
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 257
7.4.11 NMI Interrupts and DMAC.................................................................................. 258
7.4.12 Aborting a DMAC Transfer................................................................................. 259
7.4.13 Exiting Full Address Mode.................................................................................. 260
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode ......................... 261
7.5
Interrupts ........................................................................................................................... 262
7.6
Usage Notes ...................................................................................................................... 263
7.6.1
Note on Word Data Transfer................................................................................ 263
................................................................................................ 209
Rev. 4.00 Jan 26, 2006 page xi of xxii
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