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2003.11.7
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H8/36912
Renesas 16-Bit Single-Chip Microcomputer
,
H8/36902
Group
H8 Family/H8/300H Tiny Series
H8/36912F
H8/36902F
H8/36912
H8/36911
H8/36902
H8/36901
H8/36900
Group
Hardware Manual
HD64F36912G
HD64F36902G
HD64336912G
HD64336911G
HD64336902G
HD64336901G
HD64336900G
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Table of Contents
Related Manuals for Renesas H8/36912 Series
Summary of Contents for Renesas H8/36912 Series
- Page 1 H8/36912 H8/36902 Group Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36912F HD64F36912G H8/36902F HD64F36902G H8/36912 HD64336912G H8/36911 HD64336911G H8/36902 HD64336902G H8/36901 HD64336901G H8/36900 HD64336900G Rev.1.00 2003.11.7 Downloaded from Elcodis.com electronic components distributor...
- Page 2 Rev. 1.00, 11/03, page ii of xxviii Downloaded from Elcodis.com electronic components distributor...
- Page 3 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
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Page 4: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. - Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
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Page 6: Preface
The H8/36912 Group and H8/36902 Group are single-chip microcomputers made up of the high- speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. - Page 7 Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ H8/36912 Group and H8/36902 Group manuals: Document Title Document No. H8/36912 Group, H8/36902 Group Hardware Manual...
- Page 8 Rev. 1.00, 11/03, page viii of xxviii Downloaded from Elcodis.com electronic components distributor...
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Page 9: Table Of Contents
Contents Section 1 Overview................... 1 Features ..........................1 Internal Block Diagram.....................3 Pin Arrangement .......................5 Pin Functions........................9 Section 2 CPU....................11 Address Space and Memory Map ..................12 Register Configuration ......................14 2.2.1 General Registers ....................15 2.2.2 Program Counter (PC) ..................16 2.2.3 Condition-Code Register (CCR) ................16 Data Formats ........................18 2.3.1 General Register Data Formats ................18... - Page 10 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............. 51 Reset Exception Handling....................52 Interrupt Exception Handling.................... 53 3.4.1 External Interrupts ....................53 3.4.2 Internal Interrupts....................54 3.4.3 Interrupt Handling Sequence ................54 3.4.4 Interrupt Response Time..................56 Usage Notes ........................58 3.5.1 Interrupts after Reset....................
- Page 11 Section 6 Power-Down Modes ................. 83 Register Descriptions ......................84 6.1.1 System Control Register 1 (SYSCR1) ..............84 6.1.2 System Control Register 2 (SYSCR2) ..............86 6.1.3 Module Standby Control Register 1 (MSTCR1)..........87 6.1.4 Module Standby Control Register 2 (MSTCR2)..........88 Mode Transitions and States of LSI ..................89 6.2.1 Sleep Mode ......................90 6.2.2...
- Page 12 Port 2..........................115 9.2.1 Port Control Register 2 (PCR2) ................115 9.2.2 Port Data Register 2 (PDR2)................116 9.2.3 Pin Functions ....................... 116 Port 5..........................117 9.3.1 Port Mode Register 5 (PMR5) ................118 9.3.2 Port Control Register 5 (PCR5) ................118 9.3.3 Port Data Register 5 (PDR5)................
- Page 13 11.3.3 Timer Control Register V0 (TCRV0) ..............140 11.3.4 Timer Control/Status Register V (TCSRV) ............142 11.3.5 Timer Control Register V1 (TCRV1) ..............143 11.4 Operation...........................144 11.4.1 Timer V Operation ....................144 11.5 Timer V Application Examples..................147 11.5.1 Pulse Output with Arbitrary Duty Cycle..............147 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .....148 11.6 Usage Notes ........................149 Section 12 Timer W ..................
- Page 14 Section 14 Serial Communication Interface 3 (SCI3) ........187 14.1 Features ..........................187 14.2 Input/Output Pins ......................189 14.3 Register Descriptions ......................189 14.3.1 Receive Shift Register (RSR) ................190 14.3.2 Receive Data Register (RDR) ................190 14.3.3 Transmit Shift Register (TSR) ................190 14.3.4 Transmit Data Register (TDR)................
- Page 15 15.3.4 I C Bus Interrupt Enable Register (ICIER)............232 15.3.5 I C Bus Status Register (ICSR)................234 15.3.6 Slave Address Register (SAR) ................236 15.3.7 I C Bus Transmit Data Register (ICDRT) ............237 15.3.8 I C Bus Receive Data Register (ICDRR).............237 15.3.9 I C Bus Shift Register (ICDRS)................237 15.4 Operation...........................238 15.4.1 I...
- Page 16 17.3.2 Low-Voltage Detection Circuit................273 Section 18 Power Supply Circuit...............279 18.1 When Using Internal Power Supply Step-Down Circuit........... 279 18.2 When Not Using Internal Power Supply Step-Down Circuit..........280 Section 19 List of Registers................281 19.1 Register Addresses (Address Order) ................. 282 19.2 Register Bits........................
- Page 17 Appendix B I/O Port Block Diagrams .............. 355 I/O Port Block Diagrams....................355 Port States in Each Operating State...................369 Appendix C Product Code Lineup..............370 Appendix D Package Dimensions ..............371 Index ......................373 Rev. 1.00, 11/03, page xvii of xxviii Downloaded from Elcodis.com electronic components distributor...
- Page 18 Rev. 1.00, 11/03, page xviii of xxviii Downloaded from Elcodis.com electronic components distributor...
- Page 19 Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8/36912 Group..............3 Figure 1.2 Internal Block Diagram of H8/36902 Group..............4 Figure 1.3 Pin Arrangement of H8/36912 Group (LQFP-32)............5 Figure 1.4 Pin Arrangement of H8/36902 Group (LQFP-32)............6 Figure 1.5 Pin Arrangement of H8/36912 Group (SOP-32) ............7 Figure 1.6 Pin Arrangement of H8/36902 Group (SOP-32) ............8 Section 2 CPU Figure 2.1 Memory Map (1) ......................12...
- Page 20 Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1) (From Internal RC Clock to External Clock)............... 73 Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (From External Clock to Internal RC Clock)............... 74 Figure 5.6 Timing Chart of Switching Internal RC Clock to External Clock....... 75 Figure 5.7 Timing Chart to Switch External Clock to Internal RC Clock ........
- Page 21 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input........148 Figure 11.11 Contention between TCNTV Write and Clear ............149 Figure 11.12 Contention between TCORA Write and Compare Match ........150 Figure 11.13 Internal Clock Switching and TCNTV Operation ..........150 Section 12 Timer W Figure 12.1 Timer W Block Diagram ..................153 Figure 12.2 Free-Running Counter Operation ................164 Figure 12.3 Periodic Counter Operation ..................165...
- Page 22 Figure 14.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits) ....202 Figure 14.5 Sample SCI3 Initialization Flowchart ..............203 Figure 14.6 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ................204 Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)......
- Page 23 Figure 15.18 Sample Flowchart for Master Receive Mode ............250 Figure 15.19 Sample Flowchart for Slave Transmit Mode............251 Figure 15.20 Sample Flowchart for Slave Receive Mode ............252 Figure 15.21 Timing of Bit Synchronous Circuit ...............254 Section 16 A/D Converter Figure 16.1 Block Diagram of A/D Converter................256 Figure 16.2 A/D Conversion Timing ..................262 Figure 16.3 External Trigger Input Timing.................263 Figure 16.4 A/D Conversion Accuracy Definitions (1) ..............264...
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Page 24: Appendix
Figure B.9 Port 7 Block Diagram (P75) ..................362 Figure B.10 Port 7 Block Diagram (P74) ................... 363 Figure B.11 Port 8 Block Diagram (P84 to P81) ................ 364 Figure B.12 Port 8 Block Diagram (P80) ................... 365 Figure B.13 Port B Block Diagram (PB3,PB2) ................366 Figure B.14 Port B Block Diagram (PB1, PB0) ................. - Page 25 Tables Section 1 Overview Table 1.1 Pin Functions ........................9 Section 2 CPU Table 2.1 Operation Notation......................21 Table 2.2 Data Transfer Instructions...................22 Table 2.3 Arithmetic Operations Instructions (1) ...............23 Table 2.3 Arithmetic Operations Instructions (2) ...............24 Table 2.4 Logic Operations Instructions ..................24 Table 2.5 Shift Instructions......................25 Table 2.6...
- Page 26 Section 10 Timer B1 Table 10.1 Timer B1 Operating Modes .................. 136 Section 11 Timer V Table 11.1 Pin Configuration....................138 Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions ....... 141 Section 12 Timer W Table 12.1 Timer W Functions ....................
- Page 27 Table 20.10 Power-On Reset Circuit Characteristics..............305 Table 20.11 Flash Memory Characteristics................306 Table 20.12 DC Characteristics (1)...................310 Table 20.12 DC Characteristics (2)...................314 Table 20.13 AC Characteristics ....................315 Table 20.14 C Bus Interface Timing ..................316 Table 20.15 Serial Interface (SCI3) Timing................317 Table 20.16 A/D Converter Characteristics ................318 Table 20.17 Watchdog Timer Characteristics................319...
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Page 29: Section 1 Overview
HD64336900G 2 kbytes 256 bytes Under planning Note: F-ZTAT is a trademark of Renesas Technology Corp. • General I/O ports Eighteen I/O pins, including five large-current ports (I = 20 mA, @V = 1.5 V) Four input only pins (also used for analog input) Rev. - Page 30 • Supports various power-down modes • Compact package Package Code Body Size Pin Pitch Remarks × LQFP-32 7.0 mm 0.8 mm Under development × SOP-32 FP-32D 11.3 20.45 mm 1.27 mm Rev. 1.00, 11/03, page 2 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 31: Internal Block Diagram
Internal Block Diagram E10T_0 E10T_1 E10T_2 System Internal clock H8/300H generator oscillator Data bus (lower) P17/ /TRGV P14/ P76/TMOV P75/TMCIV P74/TMRIV SCI3 Timer W P84/FTIOD P83/FTIOC P22/TXD Timer V P82/FTIOB P21/RXD bus interface P81/FTIOA P20/SCK3 P80/FTCI Watchdog Timer B1 timer P57/SCL P56/SDA POR &... -
Page 32: Figure 1.2 Internal Block Diagram Of H8/36902 Group
E10T_0 E10T_1 E10T_2 System Internal clock H8/300H generator oscillator Data bus (lower) P17/ /TRGV P14/ P76/TMOV P75/TMCIV P74/TMRIV P22/TXD P21/RXD SCI3 Timer W P20/SCK3 P84/FTIOD P83/FTIOC Watchdog Timer V P82/FTIOB timer P81/FTIOA P80/FTCI POR & LVD converter P55/ Port C Port B Figure 1.2 Internal Block Diagram of H8/36902 Group Rev. -
Page 33: Pin Arrangement
Pin Arrangement P84/FTIOD P14/ P74/TMRIV P56/SDA P75/TMCIV P57/SCL P76/TMOV ET10_2 H8/36912 Group (Top view) PB3/AN3/ExtU E10T_1 PB2/AN2/ExtD E10T_0 PB1/AN1 P17/ /TRGV PB0/AN0 Figure 1.3 Pin Arrangement of H8/36912 Group (LQFP-32) Rev. 1.00, 11/03, page 5 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 34: Figure 1.4 Pin Arrangement Of H8/36902 Group (Lqfp-32)
P84/FTIOD P14/ P74/TMRIV P75/TMCIV P76/TMOV ET10_2 H8/36902 Group (Top view) PB3/AN3/ExtU E10T_1 PB2/AN2/ExtD E10T_0 PB1/AN1 P17/ /TRGV PB0/AN0 Figure 1.4 Pin Arrangement of H8/36902 Group (LQFP-32) Rev. 1.00, 11/03, page 6 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 35: Figure 1.5 Pin Arrangement Of H8/36912 Group (Sop-32)
PB3/AN3/ExtU P76/TMOV PB2/AN2/ExtD P75/TMCIV PB1/AN1 P74/TMRIV PB0/AN0 P84/FTIOD AVcc P83/FTIOC P82/FTIOB P81/FTIOA TEST P80/FTCI H8/36912 Group (Top view) P22/TXD PC1/OSC2/CLKOUT P21/RXD PC0/OSC1 P20/SCK3 P55/ P14/ P17/ /TRGV P56/SDA P57/SCL E10T_0 E10T_1 ET10_2 Figure 1.5 Pin Arrangement of H8/36912 Group (SOP-32) Rev. -
Page 36: Figure 1.6 Pin Arrangement Of H8/36902 Group (Sop-32)
PB3/AN3/ExtU P76/TMOV PB2/AN2/ExtD P75/TMCIV PB1/AN1 P74/TMRIV PB0/AN0 P84/FTIOD AVcc P83/FTIOC P82/FTIOB P81/FTIOA TEST P80/FTCI H8/36902 Group (Top view) P22/TXD PC1/OSC2/CLKOUT P21/RXD PC0/OSC1 P20/SCK3 P55/ P14/ P17/ /TRGV E10T_0 E10T_1 ET10_2 Figure 1.6 Pin Arrangement of H8/36902 Group (SOP-32) Rev. 1.00, 11/03, page 8 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 37: Pin Functions
Pin Functions Table 1.1 Pin Functions Pin No. Type Symbol SOP-32 LQFP-32 I/O Functions Power Input Power supply pin. Connect this pin source to the system power supply. Input Ground pin. Connect this pin to the system power supply (0 V). Input Analog power supply pin for the A/D converter. -
Page 38: Manual
Pin No. Type Symbol SOP-32 LQFP-32 Functions Timer V TMOV Output TMOV is an output pin for waveforms generated by the output compare function. TMCIV Input External event input pin TMRIV Input Counter reset input pin TRGV Input Counter start trigger input pin Timer W FTCI Input... -
Page 39: Section 2 Cpu
Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs ... -
Page 40: Address Space And Memory Map
Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. The following two figures show the memory map, respectively. H8/36912 H8/36912F H8/36902 H8/36902F (Masked ROM version (Flash memory version) (under planning)) H'0000 H'0000... -
Page 41: Figure 2.1 Memory Map (2)
H8/36911 H8/36901 H8/36900 (Masked ROM version (Masked ROM version (under planning)) (under planning)) H'0000 H'0000 Interrupt vector Interrupt vector H'0045 H'0045 H'0046 H'0046 On-chip ROM (2 kbytes) On-chip ROM H'07FF (4 kbytes) H'0FFF Not used Not used H'F600 H'F600 Internal I/O register Internal I/O register H'F77F H'F77F... -
Page 42: Register Configuration
Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR). General registers (ERn) ER7 (SP) Control registers (CR) -
Page 43: General Registers
2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. -
Page 44: Program Counter (Pc)
Free area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). - Page 45 Initial Bit Name Value Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Undefined R/W User Bit Can be written and read by software using the LDC, STC,...
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Page 46: Data Formats
Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. -
Page 47: Figure 2.5 General Register Data Formats (2)
Data Type General Data Format Register Word data Word data Longword data [Legend] ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. -
Page 48: Memory Data Formats
2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. -
Page 49: Instruction Set
Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1 Operation Notation Symbol Description General register (destination)*... -
Page 50: Table 2.2 Data Transfer Instructions
Table 2.2 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd, Cannot be used in this LSI. MOVFPE MOVTPE Rs →... -
Page 51: Table 2.3 Arithmetic Operations Instructions (1)
Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. -
Page 52: Table 2.3 Arithmetic Operations Instructions (2)
Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. -
Page 53: Table 2.5 Shift Instructions
Table 2.5 Shift Instructions Instruction Size* Function Rd (shift) → Rd SHAL B/W/L SHAR Performs an arithmetic shift on general register contents. Rd (shift) → Rd SHLL B/W/L SHLR Performs a logical shift on general register contents. ROTL B/W/L Rd (rotate) → Rd ROTR Rotates general register contents. - Page 54 Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
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Page 55: Table 2.6 Bit Manipulation Instructions (1)
Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR C ⊕... -
Page 56: Table 2.7 Branch Instructions
Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨... -
Page 57: Table 2.8 System Control Instructions
Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. -
Page 58: Basic Instruction Formats
2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.7 shows examples of instruction formats. Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. -
Page 59: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. -
Page 60: Table 2.11 Absolute Address Access Ranges
Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. -
Page 61: Figure 2.8 Branch Address Specification In Memory Indirect Mode
Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. -
Page 62: Effective Address Calculation
2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) -
Page 63: Table 2.12 Effective Address Calculation (2)
Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents [Legend] r, rm,rn : Register field op : Operation field disp : Displacement... -
Page 64: Basic Bus Cycle
Basic Bus Cycle CPU operation is synchronized by a system clock (φ). The period from a rising edge of φ to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. -
Page 65: On-Chip Peripheral Modules
2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 19.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. -
Page 66: Cpu States
CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, and standby mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. -
Page 67: Usage Notes
Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. -
Page 68: Figure 2.13 Example Of Timer Configuration With Two Registers Allocated To Same
Bit Manipulation for Two Registers Assigned to the Same Address Example 1: Bit manipulation for the timer load register and timer counter (Applicable to timer B1, not available for the H8/36902 Group.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. - Page 69 [Prior to executing BSET] Input/output Input Input Output Output Output Output Output Output Pin state High level level level level level level level level PCR5 PDR5 [BSET instruction executed] The BSET instruction is executed for port 5. BSET @PDR5 [After executing BSET] Input/output Input Input...
- Page 70 [Prior to executing BSET] The PDR5 value (H'80) is written to a work area in MOV.B #80, MOV.B R0L, @RAM0 memory (RAM0) as well as to PDR5. MOV.B R0L, @PDR5 Input/output Input Input Output Output Output Output Output Output Pin state High level level...
- Page 71 [Prior to executing BCLR] Input/output Input Input Output Output Output Output Output Output Pin state High level level level level level level level level PCR5 PDR5 [BCLR instruction executed] The BCLR instruction is executed for PCR5. BCLR @PCR5 [After executing BCLR] Input/output Output Output...
- Page 72 [Prior to executing BCLR] The PCR5 value (H'3F) is written to a work area in MOV.B #3F, MOV.B R0L, @RAM0 memory (RAM0) as well as to PCR5. MOV.B R0L, @PCR5 Input/output Input Input Output Output Output Output Output Output Pin state High level level...
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Page 73: Section 3 Exception Handling
Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. - Page 74 Vector Relative Module Exception Sources Number Vector Address Priority External interrupt IRQ0, low-voltage detection H'001C to H'001D High interrupt Reserved for system use 15, 16 H'001E to H'0021 External interrupt IRQ3 H'0022 to H'0023 H'0024 to H'0025 Reserved for system use 19, 20 H'0026 to H'0029 Timer W...
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Page 75: Register Descriptions
Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt enable register 2 (IENR2) • Interrupt flag register 1 (IRR1) •... -
Page 76: Interrupt Edge Select Register 2 (Iegr2)
3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the ADTRG and WKP5 pins. Initial Bit Name Value Description 7, 6 All 1 Reserved These bits are always read as 1. WPEG5 WKP5 Edge Select 0: Falling edge of WKP5 (ADTRG) pin input is detected... -
Page 77: Interrupt Enable Register 2 (Ienr2)
3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables timer B1 interrupts. Initial Bit Name Value Description Reserved This bit is always read as 0. Reserved Although this bit is readable/writable, it should not be set to 1. IENTB1 Timer B1 Interrupt Enable When this bit is set to 1, overflow interrupt requests of... -
Page 78: Interrupt Flag Register 1 (Irr1)
3.2.5 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests. Initial Bit Name Value Description IRRDT Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1. -
Page 79: Interrupt Flag Register 2 (Irr2)
3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 interrupt requests. Initial Bit Name Value Description Reserved This bit is always read as 0. Reserved IRRTB1 Timer B1 Interrupt Request Flag [Setting condition] When timer B1 overflows [Clearing condition]... -
Page 80: Reset Exception Handling
Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low for the specified period. To reset the chip during operation, hold the RES pin low for the specified period. -
Page 81: Interrupt Exception Handling
Interrupt Exception Handling 3.4.1 External Interrupts As external interrupts, there are NMI, IRQ3, IRQ0, and WKP5 interrupts. NMI Interrupt: NMI interrupt is requested by input falling edge to the NMI pin. NMI is the highest interrupt, and can always be accepted without depending on the I bit value in CCR. IRQ3 and IRQ0 Interrupts: IRQ3 and IRQ0 interrupts are requested by input signals to the IRQ3 and IRQ0 pins. -
Page 82: Internal Interrupts
Reset cleared Initial program instruction prefetch Vector fetch Internal processing Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to... -
Page 83: Figure 3.2 Stack Status After Exception Handling
2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. The CPU accepts the NMI or address break without depending on the I bit value. Other interrupt requests are accepted, if the I bit is cleared to 0 in CCR;... -
Page 84: Interrupt Response Time
3.4.4 Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 23 15 to 37 Saving of PC and CCR to stack... -
Page 85: Figure 3.3 Interrupt Sequence
Figure 3.3 Interrupt Sequence Rev. 1.00, 11/03, page 57 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 86: Usage Notes
Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. -
Page 87: Section 4 Address Break
Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. -
Page 88: Address Break Control Register (Abrkcr)
4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Initial Bit Name Value Description RTINTE RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. -
Page 89: Address Break Status Register (Abrksr)
When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. -
Page 90: Break Address Registers (Barh, Barl)
4.1.3 Break Address Registers (BARH, BARL) BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 4.1.4 Break Data Registers (BDRH, BDRL) BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break... -
Page 91: Operation
Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. -
Page 92: Figure 4.2 Address Break Interrupt Operation Example (2)
When the address break is specified in the data read cycle Register setting Program • ABRKCR = H'A0 0258 • BAR = H'025A 025A 025C MOV.W @H'025A,R0 0260 Underline indicates the address 0262 to be stacked. Next instruc- instruc- instruc- instruc- instruc- instruc-... -
Page 93: Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) consists of an external oscillator, an internal RC oscillator, a duty correction circuit, a clock select circuit, and system clock dividers. Figure 5.1 shows a block diagram of the clock pulse generator. φ... -
Page 94: Features
Features • Choice of two clock sources Internal RC oscillator clock External oscillator clock • Choice of two types of RC oscillation frequency by the user software 8MHz ±5% 10MHz ±5% • Frequency trimming The initial frequency of the internal RC oscillator in the flash memory version is within the range shown above, so users do not need to trim the frequency. -
Page 95: Register Descriptions
Register Descriptions Clock oscillators are controlled by the following registers. • RC control register (RCCR) • RC trimming data protect register (RCTRMDPR) • RC trimming data register (RCTRMDR) • Clock control/status register (CKCSR) 5.2.1 RC Control Register (RCCR) RCCR controls the internal RC oscillator. Initial Bit Name Value... -
Page 96: Rc Trimming Data Protect Register (Rctrmdpr)
5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Initial Bit Name Value Description Write Inhibit Only when writing 0 to this bit, this register can be written to. -
Page 97: Rc Trimming Data Register (Rctrmdr)
Initial Bit Name Value Description 3 to 0 All 1 Reserved These bits are always read as 1 5.2.3 RC Trimming Data Register (RCTRMDR) RCTRMDR stores the trimming data of the internal RC oscillator frequency. Initial Bit Name Value Description TRMD7... - Page 98 Initial Bit Name Value Description OSCBAKE 0 External Clock Backup Enable 0: External clock backup disabled 1: External clock backup enabled The detection circuit for the external clock is enabled when this bit is 1. When the external clock halt is detected while this LSI operates on the external clock, the system clock source is automatically switched to the internal RC oscillator regardless of the value of bit 4 in this register.
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Page 99: System Clock Select Operation
Initial Bit Name Value Description OSCHLT External Clock Halt Detection Flag • When OSCBAKE = 1 This bit indicates the checking result of the external clock state. 0: External oscillation is in use 1: External oscillation is halted. • When OSCBAKE = 0 This bit is meaningless. -
Page 100: Clock Control Operation
5.3.1 Clock Control Operation The LSI system clock is generated by the internal RC clock after a reset. The internal RC clock is switched to the external clock by the user software. Figure 5.3 shows the flowchart to switch clocks with the external oscillator backup function enabled. Figures 5.4 and 5.5 show the flowcharts to switch clocks with the external oscillator backup function disabled. -
Page 101: Figure 5.4 Flowchart Of Clock Switching With Backup Function Disabled (1) (From Internal Rc Clock To External Clock)
LSI operates on internal RC clock [1] External oscillation starts when pins PC1 and PC0 are selected as external oscillation pins. Write 0 to Start (reset) bit PMRC1 to input the external clock. [2] After writing 1 to the OSCSEL bit, this LSI waits until the oscillation of the external oscillator settles. -
Page 102: Figure 5.5 Flowchart Of Clock Switching With Backup Function Disabled (2) (From External Clock To Internal Rc Clock)
LSI operates on internal RC clock [1] When 0 is written to the OSCSEL bit, this LSI Start switches the external clock to the internal RC clock (LSI operates on internal RC clock) after the φ stop duration. Seven rising edges of the φ... -
Page 103: Clock Change Timing
5.3.2 Clock Change Timing The timing for changing clocks are shown in figures 5.6 to 5.8. φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA φ halt* Internal RC clock operation External clock operation Wait for external oscillation settling Nwait [Legend] φOSC: External clock φRC:... -
Page 104: Figure 5.7 Timing Chart To Switch External Clock To Internal Rc Clock
φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF External clock φ halt* External RC clock operation operation Wait for external oscillation settling Nwait [Legend] φOSC: External clock φRC: Internal RC clock φ: System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR... -
Page 105: Figure 5.8 External Oscillation Backup Timing
External clock halt φOSC φRC φ OSCHLT PHISTOP (Internal signal) CKSTA CKSWIF φ halt Internal clock φ halt* External RC clock operation operation detected* [Legend] φOSC: External clock φRC: Internal RC clock φ: System clock OSCHLT: Bit 1 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR... -
Page 106: Trimming Of Internal Rc Oscillator Frequency
Trimming of Internal RC Oscillator Frequency Users can trim the internal RC oscillator frequency, supplying the external reference pulses with the input capture function in internal timer W. An example of trimming flow and a timing chart are shown in figures 5.9 and 5.10, respectively. Because RCTRMDR is initialized by a reset, when users have trimmed the oscillators, some operations after a reset are necessary, such as trimming it again or saving the trimming value in an external device for later reloading. -
Page 107: Figure 5.10 Timing Chart Of Trimming Of Internal Rc Oscillator Frequency
φRC FTIOA input capture input (µs) Timer W M + α M + 1 M - 1 TCNT M + α Capture 1 Capture 2 Figure 5.10 Timing Chart of Trimming of Internal RC Oscillator Frequency The internal RC oscillator frequency is gained by the expression below. Since the input-capture input is sampled by the φ... -
Page 108: External Oscillators
External Oscillators This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with general ports PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external clock input ports, refer to section 5.3, System Clock Select Operation. -
Page 109: Connecting Ceramic Resonator
5.5.2 Connecting Ceramic Resonator Figure 5.13 shows an example of connecting a ceramic resonator. PC0/OSC1 C = C = 5 to 30 pF PC1/OSC2/CLKOUT Figure 5.13 Example of Connection to Ceramic Resonator 5.5.3 External Clock Input Method To use the external clock, input the external clock on pin OSC1. Figure 5.14 shows an example of connection. -
Page 110: Usage Notes
Usage Notes 5.7.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable values should be determined in consultation with the resonator element manufacturer. -
Page 111: Section 6 Power-Down Modes
Section 6 Power-Down Modes For operating modes after a reset, this LSI has not only a normal active mode but also three power-down modes in which power consumption is significantly reduced. In addition, there is also a module standby function which reduces power consumption by individually stopping on-chip peripheral modules. -
Page 112: Register Descriptions
Register Descriptions The registers related to power-down modes are listed below. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • Module standby control register 1 (MSTCR1) • Module standby control register 2 (MSTCR2) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. - Page 113 Initial Bit Name Value Description 3 to 0 All 0 Reserved These bits are always read as 0. Table 6.1 Operating Frequency and Wait Time Bit Name Operating Frequency STS2 STS1 STS0 Wait Time 10 MHz 8 MHz 5 MHz 4 MHz 2.5 MHz...
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Page 114: System Control Register 2 (Syscr2)
6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Name Value Description SMSEL Sleep Mode Selection This bit specifies the mode to be entered after executing the SLEEP instruction, as well as the SSBY bit in SYSCR1. -
Page 115: Module Standby Control Register 1 (Mstcr1)
6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Name Value Description Reserved This bit is always read as 0. MSTIIC IIC2 Module Standby IIC2 enters standby mode when this bit is set to 1. -
Page 116: Module Standby Control Register 2 (Mstcr2)
6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Name Value Description 7 to 5 All 0 Reserved These bits are always read as 0. MSTTB1 Timer B1 Module Standby Timer B1 enters standby mode when this bit is set to 1. -
Page 117: Mode Transitions And States Of Lsi
Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. -
Page 118: Sleep Mode
Table 6.3 Internal State in Each Operating Mode Function Active Mode Sleep Mode Subsleep Mode Standby Mode System clock oscillator Functioning Functioning Halted Halted Instructions Functioning Halted Halted Halted operations Registers Functioning Retained Retained Retained Functioning Retained Retained Retained IO ports Functioning Retained Retained... -
Page 119: Standby Mode
6.2.2 Standby Mode In standby mode, the system clock oscillator is halted, and operation of the CPU and on-chip peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. -
Page 120: Operating Frequency In Active Mode
Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2 to MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. Direct Transition The CPU can execute programs in active mode. The operating frequency can be changed by making a transition directly from active mode to active mode. -
Page 121: Section 7 Rom
Section 7 ROM The features of the 12-kbyte (including 4 kbytes as the E7 control program area) flash memory built into the HD64F36912G and HD64F36902G are summarized below. • Programming/erase methods The flash memory is programmed in 64-byte units at a time. Erase is performed in single- block units. -
Page 122: Block Configuration
Block Configuration Figure 7.1 shows the block configuration of 12-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 1 kbyte × 4 blocks and 4 kbytes × 2 blocks. Erasing is performed in these units. -
Page 123: Figure 7.1 Flash Memory Block Configuration
H'0000 H'0001 H'0002 H'003F Programming unit: 64 kbytes Erase unit H'0040 H'0041 H'0042 H'007F 1 kbyte H'03C0 H'03C1 H'03C2 H'03FF H'0400 H'0401 H'0402 H'043F Programming unit: 64 kbytes Erase unit H'0440 H'0441 H'0442 H'047F 1 kbyte H'07C0 H'07C1 H'07C2 H'07FF H'0800 H'0801 H'0802... -
Page 124: Register Descriptions
Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. -
Page 125: Flash Memory Control Register 2 (Flmcr2)
Initial Bit Name Value Description Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, program- verify mode is cancelled. Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory changes to erase mode. -
Page 126: Erase Block Register 1 (Ebr1)
7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. -
Page 127: On-Board Programming Modes
On-Board Programming Modes There is a mode for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. - Page 128 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset.
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Page 129: Table 7.2 Boot Mode Operation
Table 7.2 Boot Mode Operation Host Operation Communication Contents LSI Operation Processing Contents Processing Contents Branches to boot program at reset-start. Boot program initiation H'00, H'00 . . . H'00 Continuously transmits data H'00 • Measures low-level period of receive data at specified bit rate. -
Page 130: Programming/Erasing In User Program Mode
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps 8 to 10 MHz 4,800 bps 4 to 10 MHz 2,400 bps 2 to 10 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user... -
Page 131: Flash Memory Programming/Erasing
Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. -
Page 132: Figure 7.3 Program/Program-Verify Flowchart
START Write pulse application subroutine Disable WDT Apply Write Pulse Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 64-byte program data in program data area and reprogram data area Wait 50 µs n = 1 Set P bit in FLMCR1 m= 0... -
Page 133: Erase/Erase-Verify
Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments Programming completed Reprogram bit — Remains in erased state Table 7.5 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming Table 7.6... -
Page 134: Interrupt Handling When Programming/Erasing Flash Memory
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. -
Page 135: Figure 7.4 Erase/Erase-Verify Flowchart
Erase start Disable WDT SWE bit ← 1 Wait 1 µs n ← 1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 µs E bit ← 0 Wait 10 µs ESU bit ← 10 Wait 10 µs Disable WDT EV bit ←... -
Page 136: Program/Erase Protection
Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. -
Page 137: Section 8 Ram
Section 8 RAM The H8/36912F and H8/36902F have 1536 bytes, the H8/36912 and H8/36902 have 512 bytes, and the H8/36911, H8/36901, and H8/36900 have 256 bytes of on-chip high-speed static RAM, respectively. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. - Page 138 Rev. 1.00, 11/03, page 110 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 139: Section 9 I/O Ports
Section 9 I/O Ports The LSI of the H8/36912 Group and H8/36902 Group has 18 general I/O ports. Port 8 (P84 to P80) is a large current port, which can drive 20 mA (@V = 1.5 V) when a low level signal is output. -
Page 140: Port Mode Register 1 (Pmr1)
9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Name Value Description IRQ3 P17/IRQ3/TRGV Pin Function Switch Selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin ... -
Page 141: Port Control Register 1 (Pcr1)
9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Name Value Description PCR17 When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the ... -
Page 142: Port Pull-Up Control Register 1 (Pucr1)
9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Name Value Description PUCR17 Only bits for which PCR1 is cleared are valid. The pull-up MOS of the P17 and P14 pins enter the on- state when these bits are set to 1, while they enter the ... -
Page 143: Port 2
Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses. -
Page 144: Port Data Register 2 (Pdr2)
9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Initial Bit Name Value Description 7 to 3 All 1 Reserved These bits are always read as 1. These bits store output data for port 2 pins. If PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read. -
Page 145: Port 5
• P20/SCK3 pin Register SCR3 PCR2 Bit Name CKE1 CKE0 PCR20 Pin Function Setting value 0 P20 input pin P20 output pin SCK3 output pin SCK3 output pin SCK3 input pin [Legend] Don't care Port 5 Port 5 is a general I/O port also functioning as an I C bus interface I/O pin*, A/D trigger input pin, and wakeup interrupt input pin. -
Page 146: Port Mode Register 5 (Pmr5)
9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Name Value Description 7, 6 All 0 Reserved These bits are always read as 0. WKP5 P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG. -
Page 147: Port Data Register 5 (Pdr5)
9.3.3 Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5. Initial Bit Name Value Description These bits store output data for port 5 pins. If PDR5 is read while PCR5 bits are set to 1, the value stored in PDR5 are read. -
Page 148: Pin Functions
9.3.5 Pin Functions The correspondence between the register specification and the port functions is shown below. • P57/SCL pin Register ICCR PCR5 Bit Name PCR57 Pin Function Setting value P57 input pin P57 output pin SCL I/O pin* [Legend] Don't care Note: As the SCL output form is NMOS open-drain, direct bus drive is enabled. -
Page 149: Port 7
Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4. The register setting of TCSRV in timer V has priority for functions of the P76/TMOV pin. -
Page 150: Port Data Register 7 (Pdr7)
9.4.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Initial Bit Name Value Description Reserved This bit is always read as 1. These bits store output data for port 7 pins. If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 is read. -
Page 151: Port 8
• P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting value 0 P74 input/TMRIV input pin P74 output/TMRIV input pin Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. -
Page 152: Port Control Register 8 (Pcr8)
9.5.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Initial Bit Name Value Description 7 to 5 Reserved PCR84 When each of the port 8 pins, P84 to P80, functions as an general I/O port, setting a PCR8 bit to 1 makes the PCR83 corresponding pin an output port, while clearing the bit to... -
Page 153: Pin Functions
9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P84/FTIOD pin Register TIOR1 PCR8 Bit Name IOD2 IOD1 IOD0 PCR84 Pin Function Setting value 0 P84 input/FTIOD input pin P84 output/FTIOD input pin FTIOD output pin FTIOD output pin P84 input/FTIOD input pin... - Page 154 • P82/FTIOB pin Register TIOR0 PCR8 Bit Name IOB2 IOB1 IOB0 PCR82 Pin Function Setting value 0 P82 input/FTIOB input pin P82 output/FTIOB input pin FTIOB output pin FTIOB output pin P82 input/FTIOB input pin P82 output/FTIOB input pin [Legend] Don't care •...
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Page 155: Port B
Port B Port B is an input port also functioning as an A/D converter analog input pin and LVD external comparison voltage input pin. Each pin of the port B is shown in figure 9.6. PB3/AN3/ExtU PB2/AN2/ExtD Port B PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration Port B has the following register. -
Page 156: Pin Functions
9.6.2 Pin Functions The correspondence between the register specification and the port functions is shown below. • PB3/AN3/ExtU pin Register ADCSR LVDCR Bit Name VDDII Pin Function Setting value AN3 input pin AN3 input/ExtU input pin Other than the above values PB3 input pin PB3 input/ExtU input pin •... - Page 157 • PB0/AN0 pin Register ADCSR Bit Name SCAN Pin Function Setting AN0 input pin value Other than the above values PB0 input pin [Legend] Don't care Rev. 1.00, 11/03, page 129 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 158: Port C
Port C Port C is a general I/O port also functioning as an external oscillation pin and clock output pin. Each pin of the port C is shown in figure 9.7. The register setting of CKCSR has priority for functions of the pins for both uses. PC1/OSC2/CLKOUT Port C PC0/OSC1... -
Page 159: Port Control Register C (Pcrc)
9.7.1 Port Control Register C (PCRC) PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C. Initial Bit Name Value Description 7 to 2 Reserved PCRC1 When each of the port C pins, PC1 and PC0, functions as an general I/O port, setting a PCRC bit to 1 makes the PCRC0 corresponding pin an output port, while clearing the bit to... - Page 160 • PC0/OSC1 pin Register CKCSR PCRC Bit Name PMRC0 PCRC0 Pin Function Setting value PC0 input pin PC0 output pin OSC1 oscillation pin [Legend] Don't care Rev. 1.00, 11/03, page 132 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 161: Section 10 Timer B1
Section 10 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 10.1 shows a block diagram of timer B1. 10.1 Features •... -
Page 162: Register Descriptions
10.2 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 10.2.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Initial Value Bit Name... -
Page 163: Timer Counter B1 (Tcb1)
10.2.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. -
Page 164: Operation
10.3 Operation 10.3.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately. -
Page 165: Section 11 Timer V
Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. -
Page 166: Input/Output Pins
TCRV1 TCORB Trigger TRGV control Comparator Clock select TMCIV TCNTV Comparator TCORA Clear TCRV0 TMRIV control Interrupt request control Output TCSRV TMOV control CMIA CMIB [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0:... -
Page 167: Register Descriptions
11.3 Register Descriptions Time V has the following registers. • Timer counter V (TCNTV) • Timer constant register A (TCORA) • Timer constant register B (TCORB) • Timer control register V0 (TCRV0) • Timer control/status register V (TCSRV) • Timer control register V1 (TCRV1) 11.3.1 Timer Counter V (TCNTV) TCNTV is an 8-bit up-counter. -
Page 168: Timer Control Register V0 (Tcrv0)
11.3.3 Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Initial Bit Name Value Description CMIEB Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled. -
Page 169: Table 11.2 Clock Signals To Input To Tcntv And Counting Conditions
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 CKS2 CKS1 CKS0 ICKS0 Description Clock input prohibited Internal clock: counts on φ/4, falling edge Internal clock: counts on φ/8, falling edge Internal clock: counts on φ/16, falling edge Internal clock: counts on φ/32, falling edge Internal clock: counts on φ/64, falling edge... -
Page 170: Timer Control/Status Register V (Tcsrv)
11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Name Value Description CMFB Compare Match Flag B [Setting condition] When the TCNTV value matches the TCORB value [Clearing condition] After reading CMFB = 1, cleared by writing 0 to CMFB CMFA Compare Match Flag A... -
Page 171: Timer Control Register V1 (Tcrv1)
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match. 11.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to... -
Page 172: Operation
11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal selected, and figure 11.3 shows the count timing with both edges of an external clock signal selected. -
Page 173: Figure 11.3 Increment Timing With External Clock
TMCIV (External clock input pin) TCNTV input clock N – 1 N + 1 TCNTV Figure 11.3 Increment Timing with External Clock TCNTV H'FF H'00 Overflow signal Figure 11.4 OVF Set Timing TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing Rev. -
Page 174: Figure 11.6 Tmov Output Timing
Compare match A signal Timer V output Figure 11.6 TMOV Output Timing Compare match A signal H'00 TCNTV Figure 11.7 Clear Timing by Compare Match Compare match A signal Timer V output N – 1 H'00 TCNTV Figure 11.8 Clear Timing by TMRIV Input Rev. -
Page 175: Timer V Application Examples
11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. -
Page 176: Pulse Output With Arbitrary Pulse Width And Delay From Trgv Input
11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1. -
Page 177: Usage Notes
11.6 Usage Notes The following types of contention or operation can occur in timer V operation. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. -
Page 178: Figure 11.12 Contention Between Tcora Write And Compare Match
TCORA write cycle by CPU TCORA address Address Internal write signal TCNTV TCORA TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Write to CKS1 and CKS0 Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. -
Page 179: Section 12 Timer W
Section 12 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems. 12.1 Features •... -
Page 180: Table 12.1 Timer W Functions
Table 12.1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Count clock Internal clocks: φ, φ/2, φ/4, φ/8 External clock: FTCI General registers Period GRC (buffer GRD (buffer (output compare/input specified in register for register for capture registers) GRA in GRB in buffer buffer mode) -
Page 181: Input/Output Pins
Internal clock: FTIOA Clock FTIOB selector FTIOC Control logic External clock: FTCI FTIOD Comparator IRRTW Internal data bus [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bits) TIOR:... -
Page 182: Register Descriptions
12.3 Register Descriptions The timer W has the following registers. • Timer mode register W (TMRW) • Timer control register W (TCRW) • Timer interrupt enable register W (TIERW) • Timer status register W (TSRW) • Timer I/O control register 0 (TIOR0) •... -
Page 183: Timer Mode Register W (Tmrw)
12.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Initial Bit Name Value Description Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. ... -
Page 184: Timer Control Register W (Tcrw)
12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Initial Bit Name Value Description CCLR Counter Clear The TCNT value is cleared by compare match A when this bit is 1. -
Page 185: Timer Interrupt Enable Register W (Tierw)
Initial Bit Name Value Description Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* [Legend] Don't care Note: * The change of the setting is immediately reflected in the output value. -
Page 186: Timer Status Register W (Tsrw)
12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Initial Bit Name Value Description Timer Overflow Flag [Setting condition] • When TCNT overflows from H'FFFF to H'0000 [Clearing condition] • Read OVF when OVF = 1, then write 0 in OVF ... - Page 187 Initial Bit Name Value Description IMFB Input Capture/Compare Match Flag B [Setting conditions] • TCNT = GRB when GRB functions as an output compare register • The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition] •...
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Page 188: Timer I/O Control Register 0 (Tior0)
12.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Initial Bit Name Value Description Reserved This bit is always read as 1. IOB2 I/O Control B2 Selects the GRB function. -
Page 189: Timer I/O Control Register 1 (Tior1)
Initial Bit Name Value Description IOA1 I/O Control A1 and A0 IOA0 When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1,... - Page 190 Initial Bit Name Value Description IOD1 I/O Control D1 and D0 IOD0 When IOD2 = 0, 00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD2 = 1,...
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Page 191: Timer Counter (Tcnt)
12.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. -
Page 192: Operation
12.4 Operation The timer W has the following operating modes. • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free- running counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. -
Page 193: Figure 12.3 Periodic Counter Operation
TCNT value H'0000 Time CTS bit Flag cleared by software IMFA Figure 12.3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 12.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B. -
Page 194: Figure 12.5 Toggle Output Example (Toa = 0, Tob = 1)
TCNT value H'FFFF Time H'0000 Toggle output FTIOA Toggle output FTIOB Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B. TCNT value Counter cleared by compare match with GRA H'FFFF... -
Page 195: Figure 12.7 Input Capture Operating Example
TCNT value H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 Time FTIOA H'1000 H'F000 H'55AA FTIOB H'AA55 Figure 12.7 Input Capture Operating Example Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. -
Page 196: Pwm Operation
12.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. -
Page 197: Figure 12.10 Pwm Mode Example (2)
TCNT value Counter cleared by compare match A H'0000 Time FTIOB FTIOC FTIOD Figure 12.10 PWM Mode Example (2) Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. -
Page 198: Figure 12.12 Pwm Mode Example
TCNT value Write to GRB Write to GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously. Write to GRB Write to GRB Write to GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register... -
Page 199: Figure 12.13 Pwm Mode Example
TCNT value Write to GRB Write to GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously. Write to GRB Write to GRB Write to GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register... -
Page 200: Operation Timing
12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted correctly. -
Page 201: Output Compare Output Timing
12.5.2 Output Compare Output Timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). -
Page 202: Input Capture Timing
12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. -
Page 203: Buffer Operation Timing
12.5.5 Buffer Operation Timing Figures 12.19 and 12.20 show the buffer operation timing. Compare match signal TCNT GRC, GRD GRA, GRB Figure 12.19 Buffer Operation Timing (Compare Match) Input capture signal TCNT GRA, GRB GRC, GRD Figure 12.20 Buffer Operation Timing (Input Capture) Rev. -
Page 204: Timing Of Imfa To Imfd Flag Setting At Compare Match
12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. -
Page 205: Timing Of Imfa To Imfd Setting At Input Capture
12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture. -
Page 206: Usage Notes
12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2. -
Page 207: Figure 12.24 Contention Between Tcnt Write And Clear
TCNT write cycle TCNT address Address Write signal Counter clear signal H'0000 TCNT Figure 12.24 Contention between TCNT Write and Clear Clock before switching Clock after switching Count clock TCNT The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. -
Page 208: Figure 12.26 When Compare Match And Bit Manipulation Instruction To Tcrw Occur
TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B. When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low;... -
Page 209: Section 13 Watchdog Timer
Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1. WDT dedicated TCSRWD internal oscillator... -
Page 210: Register Descriptions
13.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. - Page 211 Initial Bit Name Value Description WDON Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. The watchdog timer is enabled in the initial state. When the watchdog timer is not used, clear the WDON bit to 0.
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Page 212: Timer Counter Wd (Tcwd)
13.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. -
Page 213: Operation
13.3 Operation The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. The internal reset signal is output for a period of 256 φ clock cycles. - Page 214 Rev. 1.00, 11/03, page 186 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 215: Section 14 Serial Communication Interface 3 (Sci3)
Section 14 Serial Communication Interface 3 (SCI3) This LSI includes serial communication interface 3 (SCI3). SCI3 can handle both asynchronous and clocked synchronous serial communication. In asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). -
Page 216: Figure 14.1 Block Diagram Of Sci3
External SCK3 Internal clock ( /64, /16, /4, ) clock Baud rate generator Clock SCR3 Transmit/receive control circuit SPMR Noise filter circuit Interrupt request (TEI, TXI, RXI, ERI) [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR:... -
Page 217: Input/Output Pins
14.2 Input/Output Pins Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration Pin Name Abbreviation Function SCI3 clock SCK3 Input/output SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output 14.3 Register Descriptions SCI3 has the following registers for each channel. -
Page 218: Receive Shift Register (Rsr)
14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. -
Page 219: Serial Mode Register (Smr)
14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock source. Initial Bit Name Value Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. -
Page 220: Serial Control Register 3 (Scr3)
Initial Bit Name Value Description CKS1 Clock Select 0 and 1 CKS0 These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 14.3.8, Bit Rate Register... - Page 221 Initial Bit Name Value Description TEIE Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. CKE1 Clock Enable 0 and 1 CKE0 Selects the clock source. • Asynchronous mode 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin.
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Page 222: Serial Status Register (Ssr)
14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Initial Bit Name Value Description TDRE Transmit Data Register Empty... - Page 223 Initial Bit Name Value Description Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] • When 0 is written to PER after reading PER = 1 TEND Transmit End [Setting conditions] • When the TE bit in SCR3 is 0 •...
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Page 224: Bit Rate Register (Brr)
14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. -
Page 225: Table 14.2 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ φ φ φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 0.16 0.21 0.00... - Page 226 Operating Frequency φ φ φ φ (MHz) 6.144 7.3728 Error Error Error Bit Rate (bit/s) –0.44 0.08 –0.07 0.16 0.00 0.00 0.16 0.00 0.00 0.16 0.00 0.00 1200 0.16 0.00 0.00 2400 0.16 0.00 0.00 4800 0.16 0.00 0.00 9600 –2.34 0.00 0.00...
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Page 227: Table 14.3 Maximum Bit Rate For Each Frequency (Asynchronous Mode)
Operating Frequency φ φ φ φ (MHz) 9.8304 Bit Rate Error (%) Error (%) Error (%) (bit/s) 0.03 –0.26 –0.25 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16 4800 0.16 0.00 0.16 9600 0.16... -
Page 228: Table 14.4 Examples Of Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ φ φ φ (MHz) Bit Rate (bit/s) — — — — — — — — — — — — 2.5k 100k 250k 500k — —... -
Page 229: Sampling Mode Register (Spmr)
14.3.9 Sampling Mode Register (SPMR) SPMR controls the serial communication function. Initial Bit Name Value Description 7 to 3 All 1 Reserved These bits are always read as 1. STDSPM Noise Filter Function Select Selects the noise filter function for the RXD pin in asynchronous mode. -
Page 230: Operation In Asynchronous Mode
14.4 Operation in Asynchronous Mode Figure 14.3 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex. -
Page 231: Sci3 Initialization
14.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. -
Page 232: Data Transmission
14.4.3 Data Transmission Figure 14.6 shows an example of operation for transmission in asynchronous mode. In transmission, SCI3 operates as described below. 1. SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. -
Page 233: Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)
Start transmission [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is Read TDRE flag in SSR written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, TDRE = 1 read 1 from the TDRE flag to... -
Page 234: Serial Data Reception
14.4.4 Serial Data Reception Figure 14.8 shows an example of operation for reception in asynchronous mode. In serial reception, SCI3 operates as described below. 1. SCI3 monitors the communication line. If a start bit is detected, SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. -
Page 235: Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode)
Table 14.5 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* Receive Data Receive Error Type Lost Overrun error Transferred to RDR Framing error Transferred to RDR Parity error Lost Overrun error + framing error Lost Overrun error + parity error Transferred to RDR Framing error + parity error Lost... -
Page 236: Operation In Clocked Synchronous Mode
14.5 Operation in Clocked Synchronous Mode Figure 14.10 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next. -
Page 237: Serial Data Transmission
14.5.3 Serial Data Transmission Figure 14.11 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, SCI3 operates as described below. 1. SCI3 monitors the TDRE flag in SSR, and if the flag is 0, SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. -
Page 238: Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
Start transmission Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag Read TDRE flag in SSR is automatically cleared to 0 and clocks are output to start the data transmission. -
Page 239: Serial Data Reception (Clocked Synchronous Mode)
14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.13 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, SCI3 operates as described below. SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. -
Page 240: Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
Start reception Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read OER flag in SSR Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF OER = 1 flag is automatically cleared to 0. -
Page 241: Simultaneous Serial Data Transmission And Reception
14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.15 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. -
Page 242: Figure 14.15 Sample Flowchart Of Simultaneous Serial Transmit And Receive Operations (Clocked Synchronous Mode)
Read SSR and check that the TDRE flag is set to 1, then write transmit Start transmission/reception data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to Read TDRE flag in SSR Read SSR and check that the RDRF flag is set to 1, then read the receive TDRE = 1 data in RDR. -
Page 243: Multiprocessor Communication Function
14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. -
Page 244: Figure 14.16 Example Of Inter-Processor Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)
Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to... -
Page 245: Multiprocessor Serial Data Transmission
14.6.1 Multiprocessor Serial Data Transmission Figure 14.17 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode. -
Page 246: Multiprocessor Serial Data Reception
14.6.2 Multiprocessor Serial Data Reception Figure 14.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. -
Page 247: Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1)
Set the MPIE bit in SCR3 to 1. Start reception Read OER and FER in SSR to check for errors. Receive error processing is performed Set MPIE bit in SCR3 to 1 in cases where a receive error occurs. Read SSR and check that the RDRF flag is Read OER and FER flags in SSR set to 1, then read the receive data in RDR and compare it with this station’s ID. -
Page 248: Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2)
Error processing OER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear OER, and FER flags in SSR to 0 <End> Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.00, 11/03, page 220 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 249: Figure 14.19 Example Of Sci3 Reception Using Multiprocessor Format (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI interrupt RDRF flag RXI interrupt request operation request cleared is not generated, and MPIE cleared to 0 RDR retains its state to 0 User... -
Page 250: Interrupts
14.7 Interrupts SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.6 SCI3 Interrupt Requests Interrupt Requests Abbreviation Interrupt Sources Receive Data Full... -
Page 251: Usage Notes
14.8 Usage Notes 14.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag. -
Page 252: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. -
Page 253: Section 15 I C Bus Interface 2 (Iic2)
Section 15 I C Bus Interface 2 (IIC2) The I C bus interface 2 conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however. -
Page 254: Figure 15.1 Block Diagram Of I
Transfer clock generation circuit Transmit/ ICCR1 receive control circuit Output ICCR2 control ICMR Noise canceler ICDRT Output ICDRS control Address Noise canceler comparator ICDRR Bus state decision circuit Arbitration ICSR decision circuit ICIER [Legend] ICCR1: C bus control register 1 Interrupt Interrupt request ICCR2:... -
Page 255: Input/Output Pins
SCL in SDA in SCL in SCL in (Master) SDA in SDA in (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I C bus interface 2. Table 15.1 Pin Configuration Name Abbreviation... -
Page 256: C Bus Control Register 1 (Iccr1)
15.3.1 C Bus Control Register 1 (ICCR1) ICCR1 enables or disables the I C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Name Initial Value R/W Description C Bus Interface Enable 0: This module is halted. -
Page 257: C Bus Control Register 2 (Iccr2)
Table 15.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate Clock φ φ φ φ = 5 MHz φ φ φ φ = 8 MHz φ φ φ φ = 10 MHz CKS3 CKS2 CKS1 CKS0 φ/28 179 kHz 286 kHz... - Page 258 Bit Bit Name Initial Value R/W Description R/W Start/Stop Issue Condition Disable The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
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Page 259: C Bus Mode Register (Icmr)
15.3.3 C Bus Mode Register (ICMR) ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bit Bit Name Initial Value R/W Description R/W MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. -
Page 260: C Bus Interrupt Enable Register (Icier)
Bit Bit Name Initial Value R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. - Page 261 Bit Bit Name Initial Value R/W Description R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) with the clocked synchronous format, when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.
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Page 262: C Bus Status Register (Icsr)
Bit Bit Name Initial Value R/W Description ACKBT R/W Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. 15.3.5 C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status. - Page 263 Bit Bit Name Initial Value R/W Description RDRF R/W Receive Data Register Full [Setting condition] • When a receive data is transferred from ICDRS to ICDRR [Clearing conditions] • When 0 is written in RDRF after reading RDRF = 1 •...
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Page 264: Slave Address Register (Sar)
Bit Bit Name Initial Value R/W Description R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] • When the slave address is detected in slave receive mode •... -
Page 265: C Bus Transmit Data Register (Icdrt)
15.3.7 C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. -
Page 266: Operation
15.4 Operation The I C bus interface can communicate either in I C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 C Bus Format Figure 15.3 shows the I C bus formats. Figure 15.4 shows the I C bus timing. -
Page 267: Master Transmit Operation
15.4.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 15.5 and 15.6. The transmission procedure and operations in master transmit mode are described below. -
Page 268: Figure 15.5 Master Transmit Mode Operation Timing (1)
(Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address (Slave output) TDRE TEND ICDRT Address + R/ Data 1 Data 2 ICDRS Address + R/ Data 1 User [2] Instruction of start... -
Page 269: Master Receive Operation
15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown below. -
Page 270: Figure 15.7 Master Receive Mode Operation Timing (1)
Master transmit mode Master receive mode (Master output) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Slave output) TDRE TEND RDRF ICDRS Data 1 ICDRR Data 1 User [3] Read ICDRR [2] Read ICDRR (dummy read) processing... -
Page 271: Slave Transmit Operation
15.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 15.9 and 15.10. The transmission procedure and operations in slave transmit mode are described below. -
Page 272: Slave Receive Operation
Slave receive mode Slave transmit mode (Master output) (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Slave output) TDRE TEND ICDRT ICDRS Data n ICDRR User [5] Clear TDRE [4] Read ICDRR (dummy read) processing [3] Clear TEND... -
Page 273: Figure 15.11 Slave Receive Mode Operation Timing (1)
(Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Master output) (Slave output) (Slave output) RDRF ICDRS Data 1 Data 2 ICDRR Data 1 User processing [2] Read ICDRR [2] Read ICDRR (dummy read) Figure 15.11 Slave Receive Mode Operation Timing (1) (Master output) -
Page 274: Clocked Synchronous Serial Format
15.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. -
Page 275: Figure 15.14 Transmit Mode Operation Timing
Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 0 Bit 1 (Output) TDRE Data 1 ICDRT Data 2 Data 3 Data 1 Data 2 Data 3 ICDRS User [3] Write data [3] Write data [3] Write data [3] Write data processing to ICDRT... -
Page 276: Noise Canceler
Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 0 Bit 1 (Input) RDRF Data 2 Data 3 Data 1 ICDRS Data 2 ICDRR Data 1 User [2] Set MST [3] Read ICDRR [3] Read ICDRR processing (when outputting the clock) Figure 15.15 Receive Mode Operation Timing... -
Page 277: Example Of Use
15.4.8 Example of Use Flowcharts in respective modes that use the I C bus interface are shown in figures 15.17 to 15.20. Start Initialize [1] Test the status of the SCL and SDA lines. Read BBSY in ICCR2 [2] Set master transmit mode. BBSY=0 ? [3] Issue the start candition. -
Page 278: Figure 15.18 Sample Flowchart For Master Receive Mode
Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR [2] Set acknowledge to the transmit device.* Clear TRS in ICCR1 to 0 Clear TDRE in ICSR [3] Dummy-read ICDDR.* [4] Wait for 1 byte to be received Clear ACKBT in ICIER to 0 [5] Check whether it is the (last receive - 1). -
Page 279: Figure 15.19 Sample Flowchart For Slave Transmit Mode
[1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. Write transmit data in ICDRT [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. -
Page 280: Figure 15.20 Sample Flowchart For Slave Receive Mode
Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [2] Set acknowledge to the transmit device. Clear ACKBT in ICIER to 0 [3] Dummy-read ICDRR. Dummy-read ICDRR [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR [6] Read the receive data. -
Page 281: Interrupts
15.5 Interrupts There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 15.3 shows the contents of each interrupt request. Table 15.3 Interrupt Requests Clocked Synchronous Interrupt Request Abbreviation... -
Page 282: Bit Synchronous Circuit
15.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull- up resistance) Therefore, it monitors SCL and communicates by bit with synchronization. -
Page 283: Section 16 A/D Converter
Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1. 16.1 Features • 10-bit resolution •... -
Page 284: Figure 16.1 Block Diagram Of A/D Converter
Internal data bus Module data bus 10-bit D/A Control circuit Comparator Sample-and- hold circuit interrupt request [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 16.1 Block Diagram of A/D Converter Rev. -
Page 285: Input/Output Pins
16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. Table 16.1 Pin Configuration Pin Name Symbol Function Analog power supply pin Input Analog block power supply pin Analog input pin 0 Input Analog input pins Analog input pin 1 Input Analog input pin 2... -
Page 286: A/D Control/Status Register (Adcsr)
Table 16.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel A/D Data Register to Be Stored Results of A/D Conversion ADDRA ADDRB ADDRC ADDRD 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter. Initial Bit Name Value... -
Page 287: A/D Control Register (Adcr)
Initial Bit Name Value Description Clock Select Selects the A/D conversions time 0: Conversion time = 134 states (max.) 1: Conversion time = 70 states (max.) Clear the ADST bit to 0 before switching the conversion time. Channel Select 0 to 2 Select analog input channels. - Page 288 Initial Bit Name Value Description — Reserved This bit is always read as 1. — Reserved Although this bit is readable/writable, it should not be set to 1. Rev. 1.00, 11/03, page 260 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 289: Operation
16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. -
Page 290: Input Sampling And A/D Conversion Time
16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) has passed after the ADST bit is set to 1, then starts conversion. -
Page 291: External Trigger Input Timing
Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. A/D conversion start delay t — — Input sampling time — — — — A/D conversion time — — CONV Note: All values represent the number of states. -
Page 292: A/D Conversion Accuracy Definitions
16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). •... -
Page 293: Figure 16.5 A/D Conversion Accuracy Definitions (2)
Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 16.5 A/D Conversion Accuracy Definitions (2) Rev. 1.00, 11/03, page 265 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 294: Usage Notes
16.6 Usage Notes 16.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;... -
Page 295: Section 17 Band-Gap Circuit, Power-On Reset, And Low-Voltage Detection Circuits
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits This LSI can include a band-gap circuit (BGR, band-gap regulator), a power-on reset circuit and low-voltage detection circuit. BGR supplies a reference voltage to the internal RC oscillator and low-voltage detection circuit. Figure 17.1 shows the block diagram of how BGR is allocated. -
Page 296: Features
17.1 Features • BGR circuit Supplies stable reference voltage covering the entire operating voltage range and the operating temperature range. Reduces power consumption when BGR is disabled by setting registers. • Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. •... -
Page 297: Register Descriptions
φ Internal Noise filter reset signal circuit Power-on reset circuit Noise filter circuit External power supply LVDCR Vreset Ladder VintU network VintD ExtD Interrupt LVDSR control circuit ExtU Interrupt request VDDII VBGR [Legend] PSS: Prescaler S LVDCR: Low-voltage-detection control register LVDSR: Low-voltage-detection status register VBGR:... - Page 298 Initial Bit Name Value Description LVDE LVD Enable 0: Low-voltage detection circuit is not used (standby mode) 1: Low-voltage detection circuit is used BGRE BGR Enable 0: BGR circuit is not used (standby mode) 1: BGR circuit is used VDDII LVDR External Compared Voltage Input Inhibit 0: Use external voltage as LVDI compared voltage 1: Use internal voltage as LVDI compared voltage...
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Page 299: Low-Voltage-Detection Status Register (Lvdsr)
Table 17.1 LVDCR Settings and Select Functions LVDCR Settings Select Functions Low- Low- Voltage- Voltage- Detection Detection Power-On Fall Rise LVDE BGRE VDDII LVDSEL LVDRE LVDDE LVDUE Reset LVDR Interrupt Interrupt √ √ √ √ ... -
Page 300: Operations
17.3 Operations 17.3.1 Power-On Reset Circuit Figure 17.3 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the internal pull-up resistor (Typ. 150 kΩ). While the RES signal is driven low, the prescaler S and the entire chip retains the reset state. -
Page 301: Low-Voltage Detection Circuit
17.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detection) Circuit: Figure 17.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is enabled after a power-on reset is released. To cancel the LVDR circuit, first the LVDRE bit in LVDCR should be cleared to 0 and then the LVDE bit in LVDCR and, if necessary, the BGRE bit should be cleared to 0. - Page 302 Low Voltage Detection Interrupt (LVDI) Circuit (When Internally Generated Voltage is used for Detection): Figure 17.5 shows the timing of the operation of the LVDI circuit. The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF bit and LVDUF bit in LVDSR must be cleared to 0 and then the LVDDE bit or LVDUE bit in LVDCR must be set to 1.
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Page 303: Figure 17.5 Operational Timing Of Lvdi Circuit
Vint (U) Vint (D) Vreset1 LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 17.5 Operational Timing of LVDI Circuit Low Voltage Detection Interrupt (LVDI) Circuit (When Voltages Input via ExtU and ExtD Pins are used for Detection): Figure 17.6 shows the timing of the LVDI circuit. -
Page 304: Figure 17.6 Operational Timing Of Lvdi Circuit (When Compared Voltage Is Input Through Extu And Extd Pins))
If the power supply voltage falls below the Vreset1 (Typ. = 2.3 V) voltage, this LSI enters low- voltage detection reset operation. When the voltages input on the ExtU and ExtD pins are used as the compared voltage, ensure to use the LVDR (reset detection voltage: Typ. = 2.3 V) circuit. External power supply voltage ExtD input voltage... -
Page 305: Figure 17.7 Timing For Enabling/Disabling Of Low-Voltage Detection Circuit
Operating Procedures for Enabling/Disabling LVDR and LVDI Circuits: The low-voltage detection circuit is enabled after reset. To enable or disable the low-voltage detection circuit correctly, follow the procedure described below. Figure 17.7 shows the timing for the operation and release of the low-voltage detection circuit. To disable the low-voltage detection circuit, clear all of the LVDRE, LVDDE, and LVDUE bits to 0. - Page 306 Rev. 1.00, 11/03, page 278 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 307: Section 18 Power Supply Circuit
Section 18 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin. -
Page 308: When Not Using Internal Power Supply Step-Down Circuit
18.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the V pin and V pin, as shown in figure 18.2. The external power supply is then input directly to the internal power supply. -
Page 309: Section 19 List Of Registers
Section 19 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) •... -
Page 310: Register Addresses (Address Order)
19.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Abbre- Module Data Bus Access Register Name viation... - Page 311 Abbre- Module Data Bus Access Register Name viation Address Name Width State General register A H'FF88 Timer W General register B H'FF8A Timer W General register C H'FF8C Timer W General register D H'FF8E Timer W Flash memory control register 1 FLMCR1 8 H'FF90 Flash memory control register 2...
- Page 312 Abbre- Module Data Bus Access Register Name viation Address Name Width State Break address register L BARL H'FFCB Address break 8 Break data register H BDRH H'FFCC Address break 8 Break data register L BDRL H'FFCD Address break 8 Port pull-up control register 1 PUCR1 H'FFD0 I/O port...
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Page 313: Register Bits
19.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0... - Page 314 Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name GRC15 GRC14 GRC13 GRC12 GRC11 GRC10 GRC9 GRC8 Timer W GRC7 GRC6 GRC5 GRC4 GRC3 GRC2 GRC1 GRC0 GRD15 GRD14 GRD13 GRD12 GRD11...
- Page 315 Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address break ABRKSR ABIF ABIE — — — — — — BARH BARH7 BARH6...
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Page 316: Register States In Each Operating Mode
19.3 Register States in Each Operating Mode Register Name Reset Active Sleep Subsleep Standby Module LVDCR Initialized — — — — LVDC LVDSR Initialized — — — — CKCSR Initialized — — — — Clock oscillator RCCR Initialized — — —... - Page 317 Register Name Reset Active Sleep Subsleep Standby Module TCRV0 Initialized — — Initialized Initialized Timer V TCSRV Initialized — — Initialized Initialized TCORA Initialized — — Initialized Initialized TCORB Initialized — — Initialized Initialized TCNTV Initialized — — Initialized Initialized TCRV1 Initialized —...
- Page 318 Register Name Reset Active Sleep Subsleep Standby Module PDRC Initialized — — — — I/O port PMR1 Initialized — — — — PMR5 Initialized — — — — PCR1 Initialized — — — — PCR2 Initialized — — — — PCR5 Initialized —...
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Page 319: Section 20 Electrical Characteristics
Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Input voltage Ports other than port B –0.3 to V +0.3 Port B –0.3 to AV... -
Page 320: Electrical Characteristics (F-Ztat Tm Version)
20.2 Electrical Characteristics (F-ZTAT Version) 20.2.1 Power Supply Voltage and Operating Ranges 1. Supply voltage and oscillation frequency range osc(MHz) 10.0 Vcc(V) AVcc = 3.0 to 5.5 V Active mode Sleep mode 2. Power supply voltage and operating frequency range (MHz) (kHz) 10.0... - Page 321 3. Analog power supply voltage and A/D converter accuracy guarantee range (MHz) 10.0 AVcc(V) Vcc = 3.0 to 5.5 V Active mode Sleep mode Rev. 1.00, 11/03, page 293 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 322: Dc Characteristics
20.2.2 DC Characteristics Table 20.2 DC Characteristics (1) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes RES, NMI, WKP5, Input high = 4.0 V to 5.5 V ×... - Page 323 Values Applicable Test Item Symbol Min. Typ. Max. Unit Notes Pins Condition Output P17, P14, = 4.0 V to 5.5 V – — — high P22 to P20, –I = 5 mA voltage P55, –I = 0.1 mA – — —...
- Page 324 Values Applicable Test Item Symbol Min. Typ. Max. Unit Notes Pins Condition –I P17, P14, P55 = 5.0 V, 50.0 — 300.0 µA Pull-up = 0.0 V current = 3.0 V, — 60.0 — µA Reference = 0.0 V value Input All input pins f = 1 MHz,...
- Page 325 Note: * Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers). RES Pin Mode Internal State Other Pins Oscillator Pins Active mode 1 Operates System clock: Internal RC oscillator Active mode 2 Operates (φ/64) Sleep mode 1 Only timers operate...
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Page 326: Table 20.2 Dc Characteristics (2)
Table 20.2 DC Characteristics (2) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise indicated. Values Application Test Item Symbol Pins Condition Min. Typ. Max. Unit Allowable output low Output pins except = 4.0 V to 5.5 V —... -
Page 327: Ac Characteristics
20.2.3 AC Characteristics Table 20.3 AC Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure System clock OSC1, OSC2 —... -
Page 328: Table 20.4 I 2 C Bus Interface Timing
Table 20.4 I C Bus Interface Timing = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure SCL input cycle time ... -
Page 329: Table 20.5 Serial Interface (Sci3) Timing
Table 20.5 Serial Interface (SCI3) Timing = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure Input Asynchro- SCK3 —... -
Page 330: A/D Converter Characteristics
20.2.4 A/D Converter Characteristics Table 20.6 A/D Converter Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes Analog power supply voltage Analog input voltage AN3 to AN0... -
Page 331: Watchdog Timer Characteristics
Values Applicable Test Item Symbol Min. Typ. Max. Unit Notes Pins Condition Conversion time (single = 4.0 V — — mode) to 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error — — ±3.5 Quantization error —... -
Page 332: Power-Supply-Voltage Detection Circuit Characteristics
20.2.6 Power-Supply-Voltage Detection Circuit Characteristics Table 20.8 Power-Supply-Voltage Detection Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Min. Typ. Max. Unit Power-supply falling detection Vint(D) LVDSEL = 0 voltage Power-supply rising detection Vint(U) LVDSEL = 0 voltage... -
Page 333: Power-On Reset Characteristics
20.2.8 Power-On Reset Characteristics Table 20.10 Power-On Reset Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Min. Typ. Max. Unit Pull-up resistance of RES pin — kΩ Power-on reset start voltage* —... -
Page 334: Flash Memory Characteristics
20.2.9 Flash Memory Characteristics Table 20.11 Flash Memory Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Test Item Symbol Condition Min. Typ. Max. Unit Programming time (per 128 bytes)* —... - Page 335 Values Test Item Symbol Condition Min. Typ. Max. Unit Erase Wait time after SWE — — µs bit setting* Wait time after ESU — — µs bit setting* Wait time after E bit — setting* α Wait time after E bit —...
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Page 336: Electrical Characteristics (Masked Rom Version)
20.3 Electrical Characteristics (Masked ROM Version) 20.3.1 Power Supply Voltage and Operating Ranges 1. Supply voltage and oscillation frequency range osc(MHz) 10.0 Vcc(V) AVcc = 3.0 to 5.5 V Active mode Sleep mode 2. Power supply voltage and operating frequency range (MHz) (kHz) 10.0... - Page 337 3. Analog power supply voltage and A/D converter accuracy guarantee range (MHz) 10.0 AVcc(V) Vcc = 2.7 to 5.5 V Active mode Sleep mode Rev. 1.00, 11/03, page 309 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 338: Dc Characteristics
20.3.2 DC Characteristics Table 20.12 DC Characteristics (1) = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes RES, NMI, WKP5, Input high = 4.0 V to 5.5 V ×... - Page 339 Values Applicable Test Item Symbol Min. Typ. Max. Unit Notes Pins Condition Output P17, P14, = 4.0 V to 5.5 V – — — high P22 to P20, –I = 5 mA voltage P55, –I = 0.1 mA – — —...
- Page 340 Values Applicable Test Item Symbol Min. Typ. Max. Unit Notes Pins Condition –I P17, P14, P55 = 5.0 V, 50.0 — 300.0 µA Pull-up = 0.0 V current = 3.0 V, — 60.0 — µA Reference = 0.0 V value Input All input pins f = 1 MHz,...
- Page 341 Note: * Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers). RES Pin Mode Internal State Other Pins Oscillator Pins Active mode 1 Operates System clock: Internal RC oscillator Active mode 2 Operates (φ/64) Sleep mode 1 Only timers operate...
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Page 342: Table 20.12 Dc Characteristics (2)
Table 20.12 DC Characteristics (2) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise indicated. Values Application Test Item Symbol Pins Condition Min. Typ. Max. Unit Allowable output low Output pins except = 4.0 V to 5.5 V —... -
Page 343: Ac Characteristics
20.3.3 AC Characteristics Table 20.13 AC Characteristics = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure System clock OSC1, OSC2 —... -
Page 344: Table 20.14 I 2 C Bus Interface Timing
Notes: 1. When an external clock is input, the minimum system clock oscillator frequency is 2.0 MHz. 2. Determined by MA2 to MA0 in system control register 2 (SYSCR2). Table 20.14 I C Bus Interface Timing = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. -
Page 345: Table 20.15 Serial Interface (Sci3) Timing
Table 20.15 Serial Interface (SCI3) Timing = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure Input Asynchro- SCK3 —... -
Page 346: A/D Converter Characteristics
20.3.4 A/D Converter Characteristics Table 20.16 A/D Converter Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes Analog power supply voltage Analog input voltage AN3 to AN0... -
Page 347: Watchdog Timer Characteristics
Values Applicable Test Item Symbol Min. Typ. Max. Unit Notes Pins Condition Conversion time (single = 4.0 V — — mode) to 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error — — ±3.5 Quantization error —... -
Page 348: Power-Supply-Voltage Detection Circuit Characteristics
20.3.6 Power-Supply-Voltage Detection Circuit Characteristics Table 20.18 Power-Supply-Voltage Detection Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Min. Typ. Max. Unit Power-supply falling detection Vint(D) LVDSEL = 0 3.3 voltage Power-supply rising detection Vint(U) LVDSEL = 0 3.6... -
Page 349: Power-On Reset Characteristics
20.3.8 Power-On Reset Characteristics Table 20.20 Power-On Reset Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Min. Typ. Max. Unit Pull-up resistance of RES pin — kΩ Power-on reset start voltage* —... -
Page 350: Operation Timing
20.4 Operation Timing OSC1 Figure 20.1 System Clock Input Timing OSC1 Figure 20.2 RES RES Low Width Timing FTCI, FTIOA FTIOB, FTIOC FTIOD TMCIV, TMRIV TRGV Figure 20.3 Input Timing Rev. 1.00, 11/03, page 322 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 351: Figure 20.4 I 2 C Bus Interface Input/Output Timing
STAH SCLH STOS STAS SCLL SDAS SDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop comdition Sr: Retransmission start condition Figure 20.4 I C Bus Interface Input/Output Timing SCKW SCK3 scyc Figure 20.5 SCK3 Input Clock Timing Rev. -
Page 352: Output Load Condition
scyc or V SCK3 or V (transmit data) (receive data) Note: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 20.7. Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode 20.5 Output Load Condition 2.4 kΩ... -
Page 353: Appendix A Instruction Set
Appendix A Instruction Set Instruction List • Operand Notation Symbol Description General (destination*) register General (source*) register General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand... - Page 354 • Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev. 1.00, 11/03, page 326 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 355: Table A.1 Instruction Set
Table A.1 Instruction Set • Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd — — — @ERs → Rd8 MOV.B @ERs, Rd —... - Page 356 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–2 → ERd32 MOV.W Rs, @–ERd — — — Rs16 → @ERd Rs16 → @aa:16 MOV.W Rs, @aa:16 — — — Rs16 → @aa:24 MOV.W Rs, @aa:24 —...
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Page 357: Arithmetic Instructions
• Arithmetic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — Rd16+#xx:16 → Rd16 ADD.W #xx:16, Rd — Rd16+Rs16 → Rd16 ADD.W Rs, Rd —... - Page 358 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–1 → ERd32 DEC.L #1, ERd — — — ERd32–2 → ERd32 DEC.L #2, ERd — — — DAS.Rd Rd8 decimal adjust — — → Rd8 Rd8 × Rs8 → Rd16 MULXU.
- Page 359 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation 0–Rd8 → Rd8 NEG.B Rd — 0–Rd16 → Rd16 NEG.W Rd — 0–ERd32 → ERd32 NEG.L ERd — 0 → (<bits 15 to 8> EXTU EXTU.W Rd —...
- Page 360 • Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
- Page 361 • Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation SHAL.B Rd — — SHAL SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR SHAR.W Rd — — SHAR.L ERd —...
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Page 362: Bit Manipulation Instructions
• Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — BSET (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —... - Page 363 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬ (#xx:3 of Rd8) → C BILD BILD #xx:3, Rd —...
- Page 364 • Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Branch Condition BRA d:8 (BT d:8) — If condition Always — — — — — — is true then BRA d:16 (BT d:16) — —...
- Page 365 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC ← ERn JMP @ERn — — — — — — — PC ← aa:24 JMP @aa:24 — — — — — — — PC ← @aa:8 JMP @@aa:8 —...
- Page 366 • System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC → @–SP TRAPA #x:2 — — — — — — TRAPA CCR → @–SP <vector> → PC CCR ← @SP+ — PC ← @SP+ —...
- Page 367 • Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation if R4L ≠ 0 then EEPMOV. B — — — — — — — EEPMOV repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 →...
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Page 368: Operation Code Map
Operation Code Map Table A.2 Operation Code Map (1) Rev. 1.00, 11/03, page 340 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 369: Table A.2 Operation Code Map (2)
Table A.2 Operation Code Map (2) Rev. 1.00, 11/03, page 341 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 370: Table A.2 Operation Code Map (3)
Table A.2 Operation Code Map (3) Rev. 1.00, 11/03, page 342 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 371: Number Of Execution States
Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. -
Page 372: Table A.3 Number Of Cycles In Each Instruction
Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access 2 or 3* Internal operation Note: * Depends on which on-chip peripheral module is accessed. -
Page 373: Table A.4 Number Of Cycles In Each Instruction
Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd... - Page 374 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16...
- Page 375 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BIOR BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD #xx:3, Rd...
- Page 376 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd...
- Page 377 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR...
- Page 378 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd...
- Page 379 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8, Rd OR.B Rs, Rd...
- Page 380 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR...
- Page 381 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd TRAPA TRAPA #xx:2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR...
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Page 382: Combinations Of Instructions And Addressing Modes
Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Addressing Mode Functions Instructions Data — — — — transfer POP, PUSH — — — — — — — — — — — — instructions MOVFPE, —... -
Page 383: Appendix B I/O Port Block Diagrams
Appendix B I/O Port Block Diagrams I/O Port Block Diagrams RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus PUCR Pull-up MOS TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR:... -
Page 384: Figure B.2 Port 1 Block Diagram (P14)
Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14) Rev. 1.00, 11/03, page 356 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 385: Figure B.3 Port 2 Block Diagram (P22)
Internal data bus SCI3 [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.3 Port 2 Block Diagram (P22) Rev. 1.00, 11/03, page 357 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 386: Figure B.4 Port 2 Block Diagram (P21)
Internal data bus SCI3 [Legend] PDR: Port data register PCR: Port control register Figure B.4 Port 2 Block Diagram (P21) Rev. 1.00, 11/03, page 358 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 387: Figure B.5 Port 2 Block Diagram (P20)
SCI3 SCKIE SCKOE Internal data bus SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P20) Rev. 1.00, 11/03, page 359 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 388: Figure B.6 (1) Port 5 Block Diagram (P57, P56) (For H8/36912 Group)
Internal data bus IIC2 SDAO/SCLO SDAI/SCLI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.6 (1) Port 5 Block Diagram (P57, P56) (for H8/36912 Group) Internal data bus [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.6 (2) Port 5 Block Diagram (P57, P56) (for H8/36902 Group) Rev. -
Page 389: Figure B.7 Port 5 Block Diagram (P55)
Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.7 Port 5 Block Diagram (P55) Rev. 1.00, 11/03, page 361 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 390: Figure B.8 Port 5 Block Diagram (P76)
Internal data bus Timer V TMOV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.8 Port 5 Block Diagram (P76) Internal data bus Timer V TMCIV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.9 Port 7 Block Diagram (P75) Rev. -
Page 391: Figure B.10 Port 7 Block Diagram (P74)
Internal data bus Timer V TMRIV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.10 Port 7 Block Diagram (P74) Rev. 1.00, 11/03, page 363 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 392: Figure B.11 Port 8 Block Diagram (P84 To P81)
Internal data bus Timer W Output control signal A to D FTIOA to D [Legend] Portdata register PDR: PCR: Portcontrol register Figure B.11 Port 8 Block Diagram (P84 to P81) Rev. 1.00, 11/03, page 364 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 393: Figure B.12 Port 8 Block Diagram (P80)
Internal data bus Timer W FTCI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.12 Port 8 Block Diagram (P80) Rev. 1.00, 11/03, page 365 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 394: Figure B.13 Port B Block Diagram (Pb3,Pb2)
Internal data bus A/D converter CH3 to CH0 SCAN Low voltage detection circuit VDDII ExtD, ExtU [Legend] Portdata register PDR: PCR: Portcontrol register Figure B.13 Port B Block Diagram (PB3,PB2) Internal data bus A/D converter SCAN CH3 to CH0 Figure B.14 Port B Block Diagram (PB1, PB0) Rev. -
Page 395: Figure B.15 Port C Block Diagram (Pc1)
Internal data bus PMRC1 PMRC0 XTALI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.15 Port C Block Diagram (PC1) Rev. 1.00, 11/03, page 367 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 396: Figure B.16 Port C Block Diagram (Pc0)
Internal data bus PMRC0 EXTALI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.16 Port C Block Diagram (PC0) Rev. 1.00, 11/03, page 368 of 376 Downloaded from Elcodis.com electronic components distributor... -
Page 397: Port States In Each Operating State
Port States in Each Operating State Port Reset Active Sleep Subsleep Standby P17, P14 High impedance Functioning Retained Retained High impedance* P22 to P20 High impedance Functioning Retained Retained High impedance P57 to P55 High impedance Functioning Retained Retained High impedance* P76 to P74 High impedance Functioning Retained... -
Page 398: Appendix C Product Code Lineup
Appendix C Product Code Lineup Product Type Product Code Model Marking Package Code H8/36912 Flash memory HD64F36912G HD64F36912G FH LQFP-32 (FP-32) version HD64F36912G TP SOP-32 (FP-32D) Masked ROM HD64336912G HD64336912G (***) FH LQFP-32 (FP-32) version HD64336912G (***) TP SOP-32 (FP-32D) H8/36911 Masked ROM HD64336911G HD64336911G (***) FH... -
Page 399: Appendix D Package Dimensions
Appendix D Package Dimensions The package dimensions that are shows in the Renesas Semiconductor Packages Data Book have priority. Unit: mm 20.45 20.95 Max 14.14 ± 0.30 1.00 Max 1.42 0 ˚ – 8 ˚ 0.10 0.80 ± 0.20 1.27 0.40 ±... - Page 400 Rev. 1.00, 11/03, page 372 of 376 Downloaded from Elcodis.com electronic components distributor...
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Page 401: Index
Index A/D converter ......... 255 Programming/erasing in user program A/D conversion time ......262 mode............102 External trigger input ......263 Software protection ......108 Sample-and-hold circuit...... 262 General registers ........15 Scan mode........... 261 I/O ports ..........111 Single mode ........261 I/O port block diagrams.......355 Acknowledge .......... - Page 402 Sleep mode ........... 90 LVDCR ....... 269, 282, 285, 288 Standby mode ........91 LVDSR ....... 271, 282, 285, 288 Subsleep mode ........91 MSTCR1 ....... 87, 284, 287, 290 Power-on reset ........267 MSTCR2 ....... 88, 284, 287, 290 Power-on reset circuit ......
- Page 403 TLB1........... 135 Overrun error........206 TMB1......134, 282, 285, 288 Parity error ..........206 TMRW......155, 282, 285, 288 Slave address...........238 TMWD......184, 283, 286, 289 Stack pointer (SP) ........15 TSR............. 190 Start condition .........238 TSRW ......158, 282, 285, 288 Stop condition .........238 Register field..........
- Page 404 Rev. 1.00, 11/03, page 376 of 376 Downloaded from Elcodis.com electronic components distributor...
- Page 405 Publication Date: Rev.1.00, November 7, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2003 Renesas Technology Corp. All rights reserved. Printed in Japan. Downloaded from Elcodis.com electronic components distributor...
- Page 406 Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd.
- Page 407 Downloaded from Elcodis.com electronic components distributor...
- Page 408 H8/36912 Group, H8/36902 Group Hardware Manual REJ09B0105-0100Z Downloaded from Elcodis.com electronic components distributor...
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