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13.2.3
Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit
7
Read/Write
The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit
data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however,
the SCI does not load the TDR contents into TSR. The CPU cannot read or write RSR directly.
13.2.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
7
Bit
Initial value
1
Read/Write
R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit data in TDR during serial transmission from TSR.
The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
5
6
6
5
1
1
R/W
R/W
R/W
Section 13 Serial Communication Interface
4
3
2
4
3
2
1
1
1
R/W
R/W
Rev. 4.00 Jan 26, 2006 page 483 of 938
1
0
0
1
1
1
R/W
R/W
REJ09B0276-0400
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