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TISRC—Timer Interrupt Status Register C
Bit:
Initial value:
Read/Write:
Overflow flag 1
Overflow flag 2
[Clearing condition]
0
Read OVF2 when OVF2 = 1, then write 0 in OVF2.
[Setting condition]
1
TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000
to H'FFFF.
Overflow interrupt enable 0
OVI0 interrupt requested by OVF0 flag is disabled
0
1
OVI0 interrupt requested by OVF0 flag is enabled
Overflow interrupt enable 1
0
OVI1 interrupt requested by OVF1 flag is disabled
1
OVI1 interrupt requested by OVF1 flag is enabled
Overflow interrupt enable 2
OVI2 interrupt requested by OVF2 flag is disabled
0
1
OVI2 interrupt requested by OVF2 flag is enabled
Note : * Only 0 can be written, to clear the flag.
7
6
5
OVIE2
OVIE1
1
0
0
R/W
R/W
Overflow flag 0
[Clearing condition]
0
Read OVF0 when OVF0 = 1, then write 0 in OVF0.
[Setting condition]
1
TCNT0 overflowed from H'FFFF to H'0000.
[Clearing condition]
0
Read OVF1 when OVF1 = 1, then write 0 in OVF1.
[Setting condition]
1
TCNT1 overflowed from H'FFFF to H'0000.
Appendix B Internal I/O Registers
H'FFF66
4
3
2
OVIE0
OVF2
OVF1
0
1
0
R/W
R/(W)*
R/(W)*
(Initial value)
(Initial value)
Rev. 4.00 Jan 26, 2006 page 837 of 938
16-bit timer (all channels)
1
0
OVF0
0
0
R/(W)*
(Initial value)
(Initial value)
(Initial value)
(Initial value)
REJ09B0276-0400
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