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Appendix B Internal I/O Registers
TCSR0—Timer Control/Status Register 0
Bit
Initial value
Read/Write
Compare match/input capture flag B
0
1
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev. 4.00 Jan 26, 2006 page 846 of 938
REJ09B0276-0400
7
6
5
4
CMFB
CMFA
OVF
ADTE
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/W
A/D trigger enable (TCSR0 only)
Bit 4
*
TRGE
ADTE
0
1
Note: * TRGE is bit 7 of the A/D control register (ADCR).
Timer overflow flag
[Clearing condition]
0
Read OVF when OVF = 1, then write 0 in OVF.
[Setting condition]
1
TCNT overflows from H'FF to H'00.
Compare match flag A
[Clearing condition]
0
Read CMFA when CMFA = 1, then write 0 in CMFA.
[Setting condition]
1
TCNT = TCORA
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
TCNT = TCORB
The TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
H'FFF82
3
2
1
OIS3
OIS2
OS1
0
0
0
R/W
R/W
R/W
Output select A1 and A0
Bit 1
Bit 0
Description
OS1
OS0
0
No change at compare match A
0
1
0 output at compare match A
0
1 output at compare match A
1
Output toggles at compare
1
match A
Output/input capture edge select B3 and B2
ICE in
Bit 3
Bit 2
Description
TCSR1
OIS3
OIS2
0
No change at compare match B
0
1
0 output at compare match B
0
0
1 output at compare match B
1
Output toggles at compare match
1
B
TCORB input capture on rising
0
edge
0
TCORB input capture on falling
1
1
edge
TCORB input capture on both
0
1
rising and falling edges
1
Description
A/D converter start requests by compare match
0
A or an external trigger are disabled
A/D converter start requests by compare match
1
A or an external trigger are enabled
A/D converter start requests by an external trigger are enabled
0
A/D converter start requests by compare match A are enabled
1
8-bit timer channel 0
0
OS0
0
R/W
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