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Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical.
Both have the structure shown in figure 9.2.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Legend
TCNT:
Timer counter (16 bits)
GRA, GRB:
General registers A and B (input capture/output compare registers) (16 bits
TCR:
Timer control register (8 bits)
TIOR:
Timer I/O control register (8 bits)
Clock selector
Comparator
Figure 9.2 Block Diagram of Channels 0 and 1
Control logic
Module data bus
Rev. 4.00 Jan 26, 2006 page 331 of 938
Section 9 16-Bit Timer
TIOCA
0
TIOCB
0
IMIA0
IMIB0
OVI0
×
2)
REJ09B0276-0400
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