System Control Register (Syscr); Table 3.2 Settings Of Bits Msd3 To Msd0 - Renesas H8SX/1520 Series Hardware Manual

Bit Bit Name

7

6

5

4

3

2

1

0
Note: Determined by pins MD1 and MD0.
*
Table 3.2
MCU Operating Mode MD1
1
2
3
3.2.2

System Control Register (SYSCR)

SYSCR controls MAC saturation operation and enables/disables the on-chip RAM and the flash
memory control registers.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Downloaded from Elcodis.com electronic components distributor
Initial Value R/W
0
1
0
1
Undefined*
Undefined*
Undefined*
Undefined*
Settings of Bits MSD3 to MSD0
0
1
1
15 14
— —
1 1
R R
7 6
FLSHE —
0 0
R/W R/W
Descriptions
R Reserved
R These are read-only bits and cannot be modified.
R
R
R
R
R
R
MD0 MDS3
1 1
0 1
1 0
13 12
MACS —
0 1
R/W R
5 4
— —
0 0
R/W R/W
Section 3 MCU Operating Modes
MDCR
MDS2 MDS1
1 0
1 0
1 0
11 10
— —
0 1
R/W R/W R/W
3 2
— —
0 0
R/W R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 69 of 804
MDS0
1
0
0
9 8
— RAME
0 1
R/W
1 0
— —
1 1
R/W
REJ09B0104-0300