Table of Contents
Advertisement
Bit 0—Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If
areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.
Bit 0
RFSHE
Description
RFSH pin refresh signal output disabled
0
(RFSH pin can be used as input/output port)
RFSH pin refresh signal output enabled
1
6.2.8
DRAM Control Register B (DRCRB)
7
Bit
MXC1
Initial value
0
Read/Write
R/W
DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column
address bits for the DRAM interface, the column address strobe output pin, enabling or disabling
of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state
insertion between RAS and CAS, and enabling or disabling of wait state insertion in refresh
cycles.
DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0.
6
5
MXC0
CSEL
RCYCE
0
0
R/W
R/W
4
3
—
0
1
R/W
—
Rev. 4.00 Jan 26, 2006 page 137 of 938
Section 6 Bus Controller
(Initial value)
2
1
TPC
RCW
0
0
R/W
R/W
REJ09B0276-0400
0
RLW
0
R/W
Advertisement
Table of Contents
