Renesas H8/3067 Series User Manual page 122

Renesas 16-bit single-chip microcomputer
Hide thumbs Also See for H8/3067 Series:
Table of Contents

Advertisement

Section 5 Interrupt Controller
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D
converter interrupt requests.
Bit 3
IPRA3
Description
0
WDT, DRAM interface, and A/D converter interrupt requests have priority level 0
(low priority)
1
WDT, DRAM interface, and A/D converter interrupt requests have priority level 1
(high priority)
Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt
requests.
Bit 2
IPRA2
Description
0
16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 0 interrupt requests have priority level 1 (high priority)
Bit 1—Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt
requests.
Bit 1
IPRA1
Description
0
16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 1 interrupt requests have priority level 1 (high priority)
Bit 0—Priority Level A0 (IPRA0): Selects the priority level of 16-bit timer channel 2 interrupt
requests.
Bit 0
IPRA0
Description
0
16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 2 interrupt requests have priority level 1 (high priority)
Rev. 4.00 Jan 26, 2006 page 98 of 938
REJ09B0276-0400
(Initial value)

Advertisement

Table of Contents
loading

This manual is also suitable for:

H8/3067H8/3066H8/3065H8/3067rf

Table of Contents