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TMDR—Timer Mode Register
Bit
Initial value
Read/Write
Phase counting mode flag
7
6
5
MDF
FDIR
1
0
0
R/W
R/W
PWM mode 0
0
1
PWM mode 1
0
Channel 1 operates normally (Initial value)
1
Channel 1 operates in PWM mode
PWM mode 2
0
Channel 2 operates normally (Initial value)
1
Channel 2 operates in PWM mode
Flag direction
OVF is set to 1 in TISRC when TCNT2
0
overflows or underflows
OVF is set to 1 in TISRC when TCNT2
1
overflows
0
Channel 2 operates normally
1
Channel 2 operates in phase counting mode
Appendix B Internal I/O Registers
H'FFF62
4
3
PWM2
1
1
R/W
Channel 0 operates normally (Initial value)
Channel 0 operates in PWM mode
(Initial value)
(Initial value)
Rev. 4.00 Jan 26, 2006 page 833 of 938
16-bit timer (all channels)
2
1
0
PWM1
PWM0
0
0
0
R/W
R/W
REJ09B0276-0400
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