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Section 8 I/O Ports
8.7.2
Register Descriptions
Table 8.10 summarizes the registers of port 6.
Table 8.10 Port 6 Registers
Address*
Name
H'EE005
Port 6 data direction register
H'FFFD5
Port 6 data register
Note: * Lower 20 bits of the address in advanced mode.
Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select
input or output for each pin in port 6.
Bit 7 is reserved. It is fixed at 1, and cannot be modified.
Bit
7
—
Initial value
1
Read/Write
—
Reserved bit
Modes 1 to 5 (Expanded Modes): P6
the clock output pin (ø) if the PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input
port if this bit is set to 1.
function as bus control output pins (LWR, HWR, RD, and AS), regardless of the
P6
to P6
6
3
settings of bits P6
DDR to P6
6
function as bus control input/output pins (BACK, BREQ, and WAIT) or input/output
P6
to P6
2
0
ports. For the method of selecting the pin functions, see table 8.11.
When P6
to P6
function as input/output ports, the pin becomes an output port if the
2
0
corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
Mode 6 and 7 (Single-Chip Mode): P6
to P6
function as generic input/output ports. P6
0
MSTCRH is cleared to 0 (initial value), and an input port if this bit is set to 1. A pin in port 6
Rev. 4.00 Jan 26, 2006 page 290 of 938
REJ09B0276-0400
6
5
P6 DDR
P6 DDR
P6 DDR
6
5
0
0
W
W
Port 6 data direction 6 to 0
These bits select input or output for port 6 pins
functions as the clock output pin (φ) or an input port. P6
7
DDR.
3
functions as the clock output pin (φ) or an input port. P6
7
7
Abbreviation
R/W
P6DDR
W
P6DR
R/W
4
3
P6 DDR
P6 DDR
4
3
2
0
0
W
W
is the clock output pin (φ) if the PSTOP bit in
Initial Value
H'80
H'80
2
1
0
P6 DDR
P6 DDR
1
0
0
0
0
W
W
W
is
7
6
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