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Appendix B Internal I/O Registers
MSTCRH—Module Standby Control Register H
7
Bit
PSTOP
0
Initial value
Read/Write
R/W
φ clock stop
Enables or disables ø clock output.
MSTCRL—Module Standby Control Register L
Bit
MSTPL7
Initial value
Read/Write
Rev. 4.00 Jan 26, 2006 page 802 of 938
REJ09B0276-0400
6
5
4
1
1
1
Reserved bits
7
6
5
MSTPL5
0
0
0
R/W
R/W
R/W
Reserved bits
H'EE01C
3
2
MSTPH2 MSTPH1 MSTPH0
1
0
R/W
R/W
Module standby H2 to H0
Selection bits for placing modules
in standby state.
H'EE01D
4
3
2
MSTPL4
MSTPL3
MSTPL2
0
0
0
R/W
R/W
R/W
Module standby L7, L5 to L2, L0
Selection bits for placing modules
in standby state.
System control
1
0
0
0
R/W
System control
1
0
MSTPL0
0
0
R/W
R/W
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