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Setting when Input Capture Occurs
• The CMFB flag is set to 1 in TCR2 and TCR3 when the ICE bit is 1 in TCSR3 and
input capture occurs.
• TMIO
pin input capture input signal edge detection is selected by bits OIS3 and OIS2
3
in TCSR2.
Counter Clear Specification
• If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in
TCR2, the 16-bit counter (both TCNT2 and TCNT3) is cleared.
• The settings of the CCLR1 and CCLR0 bits in TCR3 are ignored. The lower 8 bits
cannot be cleared independently.
OVF Flag Operation
• The OVF flag is set to 1 in TCSR2 when the 16-bit counter (TCNT2 and TCNT3)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in TCSR3 when the 16-bit counter (TCNT3) overflows (from
H'FF to H'00).
Compare Match Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to B'100 in TCR1, TCNT1 counts channel 0 compare match
A events.
Channels 0 and 1 are controlled independently. CMF flag setting, interrupt generation, TMO
pin output, counter clearing, and so on, is in accordance with the settings for each channel.
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to B'100 in TCR3, TCNT3 counts channel 2 compare match
A events.
Channels 2 and 3 are controlled independently. CMF flag setting, interrupt generation, TMO
pin output, counter clearing, and so on, is in accordance with the settings for each channel.
Caution
Do not set 16-bit count mode and compare match count mode simultaneously within the same
group, as the TCNT input clock will not be generated and the counters will not operate.
10.4.6
Input Capture Setting
The TCNT value can be transferred to TCORB on detection of an input edge on the input
capture/output compare pin (TMIO
can be selected. In 16-bit count mode, 16-bit input capture can be used.
or TMIO
). Rising edge, falling edge, or both edge detection
1
3
Section 10 8-Bit Timers
Rev. 4.00 Jan 26, 2006 page 421 of 938
REJ09B0276-0400
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