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Section 6 Bus Controller
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from
ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
φ
Address bus
RD
HWR
Data bus
(a) Idle cycle not inserted
Figure 6.44 Example of Idle Cycle Operation (2) (ICIS0 = 1)
External Address Space Access Immediately after DRAM Space Access: If a DRAM space
access is followed by a non-DRAM external access when HWR and LWR have been selected as
the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted
regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.45 shows an example of the
operation.
This is done to prevent simultaneous changing of the HWR and LWR signals used as UCAS and
LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to
the external device in the next cycle.
cycle is not inserted when PB4 and PB5 have been selected as the UCAS and LCAS output
A T
i
pins.
In the case of consecutive DRAM space access precharge cycles (T
settings are invalid. In the case of consecutive reads between different areas, for example, if the
second access is a DRAM access, only a T
this case is shown in figure 6.46.
Rev. 4.00 Jan 26, 2006 page 200 of 938
REJ09B0276-0400
Bus cycle A Bus cycle B
T
T
T
T
T
1
2
3
1
2
Data
Long buffer-off
collision
time
p
φ
Address bus
RD
HWR
Data bus
cycle is inserted, and a T
Bus cycle A Bus cycle B
T
T
T
T
T
T
1
2
3
i
1
(b) Idle cycle inserted
), the ICIS0 and ICIS1 bit
p
cycle is not. The timing in
i
2
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