Interrupt Priority Registers A And B (Ipra, Iprb) - Renesas H8/3067 Series User Manual

Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as interrupt mask bit
1 UI bit in CCR is used as user bit
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG Description
0 Interrupt is requested at falling edge of NMI input
1 Interrupt is requested at rising edge of NMI input
5.2.2

Interrupt Priority Registers A and B (IPRA, IPRB)

IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
Section 5 Interrupt Controller
Rev. 4.00 Jan 26, 2006 page 95 of 938
REJ09B0276-0400
(Initial value)
(Initial value)