Item
DMAC TEND delay time 1
TEND delay time 2
DREQ setup time
DREQ hold time
H8/3067 Group
output pin
C
A
Symbol Min
t
—
TED1
t
—
TED2
t
40
DRQS
t
10
DRQH
R
R
H
Figure 21.6 Output Load Circuit
Section 21 Electrical Characteristics
Condition
B
Max
Min
Max
100
—
50
100
—
50
—
25
—
—
10
—
C = 90 pF: ports 4, 6, 8, A
L
D
to D
15
C = 30 pF: ports 9, A, B
Ω
R = 2.4 k
L
Ω
R = 12 k
H
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
Rev. 4.00 Jan 26, 2006 page 731 of 938
Test
Unit
Conditions
ns
Figure 21.25,
figure 21.26
ns
ns
Figure 21.27
ns
to A
,
19
0
8
REJ09B0276-0400