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Section 11 Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4
and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits
7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
Address H'FFFA4
Bit
7
NDR15
Initial value
0
Read/Write
R/W
Address H'FFFA6
Bit
7
Initial value
1
Read/Write
Rev. 4.00 Jan 26, 2006 page 444 of 938
REJ09B0276-0400
6
5
NDR14
NDR13
0
0
R/W
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
6
5
1
1
Reserved bits
4
3
NDR12
0
1
R/W
4
3
NDR11
NDR10
1
0
R/W
R/W
Next data 11 to 8
These bits store the next output
data for TPC output group 2
2
1
0
1
1
1
Reserved bits
2
1
0
NDR9
NDR8
0
0
0
R/W
R/W
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