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Section 6 Bus Controller
Table 6.3
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR WCRH/WCRL
ABWn
ASTn
Wn1
0
0
—
1
0
1
1
0
—
1
0
1
Note: n = 7 to 0
6.3.3
Memory Interfaces
The H8/3067 Group memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of
DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can
be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst
ROM interface is designated functions as burst ROM space.
6.3.4
Chip Select Signals
For each of areas 0 to 7, the H8/3067 Group can output a chip select signal (CS
low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output
timing of a CSn signal.
Output of CS
CS
to CS
CS
CS
CS
CS
CS
0
3
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS
pins CS
to CS
in the input state. To output chip select signals CS
1
3
bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins CS
Rev. 4.00 Jan 26, 2006 page 148 of 938
REJ09B0276-0400
Bus Specifications (Basic Bus Interface)
Wn0
Bus Width
—
16
0
1
0
1
—
8
0
1
0
1
: Output of CS
to CS
0
Access States
2
3
2
3
is enabled or disabled in the data direction register
3
Program Wait States
0
0
1
2
3
0
0
1
2
3
to CS
) that goes
0
7
in the output state and
0
to CS
, the corresponding DDR
1
3
to
0
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