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ADRCR—Address Control Register
Bit
7
Initial value
1
Read/Write
CSCR—Chip Select Control Register
Bit
CS7E
Initial value
Read/Write
6
5
1
1
Reserved bits
ADRCTL
0
1
7
6
5
CS6E
CS5E
0
0
0
R/W
R/W
R/W
Chip select 7 to 4 enable
Bit n
CSnE
0
Output of chip select signal CSn is disabled (Initial value)
1
Output of chip select signal CSn is enabled
(n = 7 to 4)
Appendix B Internal I/O Registers
H'EE01E
4
3
2
1
1
1
Description
Address update mode 2 is selected
Address update mode 1 is selected (Initial value)
H'EE01F
4
3
2
CS4E
0
1
1
R/W
Description
Rev. 4.00 Jan 26, 2006 page 803 of 938
Bus controller
1
0
ADRCTL
1
1
R/W
Address control
Selects address update
mode 1 or address
update mode 2.
Bus controller
1
0
1
1
REJ09B0276-0400
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