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Section 7 DMA Controller
Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three
words from a 16-bit two-state access area to another 16-bit two-state access area.
CPU cycle
T
T
1
2
φ
Address
bus
RD
HWR
,
LWR
When the DMAC is activated from a DREQ pin there is a minimum interval of four states from
when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled
during the time between the transfer request and the start of the transfer. In short address mode and
normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the pin
is next sampled at the end of one block transfer.
Rev. 4.00 Jan 26, 2006 page 252 of 938
REJ09B0276-0400
T
T
T
T
T
d
1
2
1
2
Source
Destination
address
address
Figure 7.15 Burst DMA Bus Timing
DMAC cycle
T
T
T
T
T
1
2
1
2
1
CPU cycle
T
T
T
T
T
2
1
2
1
2
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