Slave Transmit Operation; Figure 15.9 Slave Transmit Mode Operation Timing (1) - Renesas H8/36912 Series User Manual

15.4.4

Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 15.9 and 15.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
Slave receive mode
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
TDRE
TEND
TRS
ICDRT
ICDRS
ICDRR
User
processing
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Slave transmit mode
9 1
Bit 7
A
Data 1
[2] Write data to ICDRT (data 1)

Figure 15.9 Slave Transmit Mode Operation Timing (1)

2 3 4 5
Bit 6 Bit 5 Bit 4 Bit 3
Data 1
[2] Write data to ICDRT (data 2)
6 7 8 9
A
Bit 2 Bit 1 Bit 0
Data 2
Data 2
[2] Write data to ICDRT (data 3)
Rev. 1.00, 11/03, page 243 of 376
1
Bit 7
Data 3