Slave Transmit Operation; Figure 16.8 Master Receive Mode Operation Timing (2) - Renesas HD6417641 Hardware Manual

SCL
9
(Master output)
SDA
A
(Master output)
SDA
(Slave output)
RDRF
RCVD
ICDRS
Data n-1
ICDRR
Data n-1
User
[5] Read ICDRR after setting RCVD
processing

Figure 16.8 Master Receive Mode Operation Timing (2)

16.4.4

Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 16.9 and 16.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS3 to CKS0 in ICCR1 to 1. (Initial setting) Set the
MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address
matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the
ninth clock pulse. At this time, if the eighth bit data (R/W) is 1, the TRS and ICSR bits in
ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The
continuous transmission is performed by writing transmit data to ICDRT every time TDRE is
set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Section 16 I
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
Data n
[7] Read ICDRR,
and clear RCVD
Rev. 4.00 Sep. 14, 2005 Page 493 of 982
2
C Bus Interface 2 (IIC2)
9
A/A
Data n
[6] Issue stop
condition
[8] Set slave
receive mode
REJ09B0023-0400