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25.3.5
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs
the transmit clock and returns an acknowledge signal. The transmit procedure and operations in
slave transmit mode are described below.
[1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according
to the operating mode.
[2] After the slave device detects a start condition, if the first frame matches its slave address, at
the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the
same time, the IRIC flag is set to 1 in ICCR, and if the IEIC bit in ICCR is set to 1 at this
time, an interrupt request is sent to the CPU. If the eighth data bit (R/
set to 1 in ICCR, automatically causing a transition to slave transmit mode. The slave device
holds SCL low from the fall of the transmit clock until data is written in ICDR.
[3] Clear the IRIC flag to 0, then write data in ICDR. The written data is transferred to ICDRS,
and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. Clear IRIC to 0,
then write the next data in ICDR. The slave device outputs the written data serially in step
with the clock output by the master device, with the timing shown in figure 25.11.
[4] When one frame of data has been transmitted, at the rise of the ninth transmit clock pulse
IRIC is set to 1 in ICCR. If the TDRE internal flag is 1, the slave device holds SCL low
from the fall of the transmit clock until data is written in ICDR. The master device drives
SDA low at the ninth clock pulse to acknowledge the data. The acknowledge signal is stored
in the ACKB bit in ICSR, and can be used to check whether the transfer was carried out
normally. If TDRE internal flag is set to 0, the data written in ICDR is transferred to ICDRS,
then transmission starts and TDRE internal flag and IRIC and IRTR flags are all set to 1
again.
[5] To continue transmitting, clear IRIC to 0, then write the next transmit data in ICDR.
Steps [4] and [5] can be repeated to transmit continuously. To end the transmission, write H'FF
in ICDR so that the SDA may be freed on the slave side. When a stop condition is detected (a
low-to-high transition of SDA while SCL is high), the BBSY flag will be cleared to 0 in ICCR.
Rev. 2.0, 11/00, page 556 of 1037
:
) is 1, the TRS bit is
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