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11.5 External signal description
The table found here describes the PORT external signal.
Name
PORTx[31:0]
Not all pins within each port are implemented on each device.
11.6 Detailed signal description
The table found here contains the detailed signal description for the PORT interface.
Table 11-3. PORT interface—detailed signal description
Signal
PORTx[31:0]
I/O
11.7 Memory map and register definition
Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
Absolute
address
(hex)
4004_9000
Pin Control Register n (PORTA_PCR0)
4004_9004
Pin Control Register n (PORTA_PCR1)
4004_9008
Pin Control Register n (PORTA_PCR2)
Freescale Semiconductor, Inc.
Table 11-2. Signal properties
Function
External interrupt
I/O
External interrupt.
State meaning
Timing
PORT memory map
Register name
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 11 Port Control and Interrupts (PORT)
I/O
Reset
I/O
NOTE
Description
Asserted—pin is logic 1.
Negated—pin is logic 0.
Assertion—may occur at any time and can assert
asynchronously to the system clock.
Negation—may occur at any time and can assert
asynchronously to the system clock.
Width
(in bits)
32
32
32
Pull
0
-
Access
Reset value
R/W
See section
11.7.1/135
R/W
See section
11.7.1/135
R/W
See section
11.7.1/135
Section/
page
129
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