Debug Mode; External Signal Description; Detailed Signal Description; Memory Map And Register Definition - NXP Semiconductors freescale KV4 Series Reference Manual

12.2.2.4 Debug mode

In Debug mode, PORT operates normally.

12.3 External signal description

The table found here describes the PORT external signal.
Name
PORTx[31:0]
Not all pins within each port are implemented on each device.

12.4 Detailed signal description

The table found here contains the detailed signal description for the PORT interface.
Table 12-2. PORT interface—detailed signal description
Signal
PORTx[31:0] I/O

12.5 Memory map and register definition

Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
Freescale Semiconductor, Inc.
Table 12-1. Signal properties
Function
External interrupt
NOTE
I/O
External interrupt.
State meaning
Timing
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 12 Port control and interrupts (PORT)
I/O Reset
I/O 0
Description
Asserted—pin is logic 1.
Negated—pin is logic 0.
Assertion—may occur at any time and can assert
asynchronously to the system clock.
Negation—may occur at any time and can assert
asynchronously to the system clock.
Pull
-
153