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5.5
Interrupt Priority Registers
There are two PIC blocks in the DSP56724/DSP56725 device, with one PIC block for each DSP core. The
PIC has also been enhanced to support additional DMA and peripheral interrupts. Two additional registers
(IPR-C1, IPR-P1) have been added to the PIC to allow an additional 12 DMA interrupts and an additional
12 peripheral interrupts.
•
IPR-C is dedicated for DSP56724/DSP56725: 4 external interrupts and the first 6 DMA channels
interrupts.
•
IPR-P is dedicated for DSP56724/DSP56725: 12 peripheral interrupt requests.
•
IPR-C1 is dedicated for an additional 12 DMA channels interrupts; only 2 additional DMA
channels are used in the DSP56724/DSP56725.
•
IPR-P1 is dedicated for an additional 12 peripheral interrupt sources; only parts of the additional
interrupts are used in the DSP56724/DSP56725.
The Interrupt Priority registers are shown in
bits are defined in
Table 5-8
vectors are shown in
Table
IPL bits
(x)xxL1
(x)xxL0
0
0
1
1
0
1
IPL bits
IxL2
IxL1
IxL0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Figure 5-1
and
Table 5-9.
The interrupt priorities are shown in
5-11.
Table 5-8. Peripherals and DMA Interrupt Priority Level Bits
Interrupts Enabled
No
Yes
Yes
Yes
Table 5-9. External Interrupts Priority Level Bits
Interrupts Enabled
No
Yes
Yes
Yes
No
Yes
Yes
Yes
through
Figure
5-8. The Interrupt Priority Level
Interrupt Priority Level
—
0
1
2
—
0
1
2
Core Configuration
Table 5-10.
The interrupt
Interrupt Priority Level
—
0
1
2
Interrupt Trigger Mode
Level Triggered
Negative Edge Triggered
5-9
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