Table 20.4 I 2 C Bus Interface Timing - Renesas H8 Series Hardware Manual

2
Table 20.4 I C Bus Interface Timing
V = 3.0 to 5.5 V, V
CC
Item
SCL input cycle time
SCL input high pulse
width
SCL input low pulse
width
SCL and SDA input fall
time
SCL and SDA input
spike pulse removal
time
SDA input bus-free
time
Start condition input
hold time
Retransmission start
condition input setup
time
Setup time for stop
condition input
Data input setup time
Data input hold time
Capacitive load of
SCL and SDA
SCL and SDA output
fall time
= 0.0 V, T = –20 to +75°C, unless otherwise indicated.
SS a
Applicable
Symbol Pins
t
SCL
t
SCLH
t
SCLL
t
Sf
t
SP
t
BUF
t
STAH
t
STAS
t
STOS
t
SDAS
t
SDAH
c
b
t V = 4.0
Sf CC
to 5.5 V
Section 20 Electrical Characteristics
Values
Test
Condition Min.
+ 600 
12t
cyc
+ 300 
3t
cyc
+ 300 
5t
cyc


5t
cyc
3t
cyc
3t
cyc
3t
cyc
1t + 20
cyc
0
0
 
 
Rev. 3.00 Sep. 14, 2006 Page 323 of 408
Reference
Typ. Max. Unit Figure

ns Figure
20.4

ns

ns

300 ns

1t ns
cyc
 
ns
 
ns
 
ns
 
ns
 
ns
 
ns

400 pF

250 ns

300 ns
REJ09B0105-0300