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Table 20.4 I
V
= 3.0 to 5.5 V, V
CC
Item
SCL input cycle time
SCL input high pulse
width
SCL input low pulse
width
SCL and SDA input fall
time
SCL and SDA input
spike pulse removal
time
SDA input bus-free
time
Start condition input
hold time
Retransmission start
condition input setup
time
Setup time for stop
condition input
Data input setup time
Data input hold time
Capacitive load of
SCL and SDA
SCL and SDA output
fall time
Rev. 1.00, 11/03, page 300 of 376
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C Bus Interface Timing
= 0.0 V, T
= –20 to +75°C, unless otherwise indicated.
SS
a
Applicable
Symbol
Pins
t
SCL
t
SCLH
t
SCLL
t
Sf
t
SP
t
BUF
t
STAH
t
STAS
t
STOS
t
SDAS
t
SDAH
c
b
t
V
Sf
CC
to 5.5 V
Test
Condition Min.
12t
cyc
600
3t
cyc
5t
cyc
5t
cyc
3t
cyc
3t
cyc
3t
cyc
1t
cyc
0
0
= 4.0
Values
Typ.
Max. Unit
+
ns
+ 300
ns
+ 300
ns
300
ns
1t
ns
cyc
ns
ns
ns
ns
+ 20
ns
ns
400
pF
250
ns
300
ns
Reference
Figure
Figure
20.4
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