Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 Details should always be checked by referring to the relevant text. H8/3847R Group, H8/3847S Group, H8/38347 Group, H8/38447 Group Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series H8/3847R Group H8/3842R H8/38347 Group H8/38342 H8/3843R...
Page 4 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 5 Notes: 1. ZTAT is a trademark of Renesas Technology Corp. 2. F-ZTAT is a trademark of Renesas Technology Corp.
Page 6 Related Material: The latest information is available at our Web Site. Please make sure that you have the most up-to-date information available. (http://www.renesas.com/) User's Manuals on the H8/3847: Manual Title Document No.
Page 7 Application Note: Manual Title Document No. H8/300L Series Application Note ADE-502-065 Rev. 6.00 Aug 04, 2006 page v of xxxvi...
Page 8 Rev. 6.00 Aug 04, 2006 page vi of xxxvi...
Page 9 Main Revisions for this Edition Item Page Revision (See Manual for Details)  “Under development” indication deleted from H8/38447 Group Preface Added Notes: 6. During a break, the watchdog timer continues to operate. Therefore, an internal reset is generated if an overflow occurs during the break.
Page 10 Item Page Revision (See Manual for Details) 8.15.1 The Description amended Management of the • If an unused pin is an output pin, handle it in one of the Un-Use Terminal following ways:  Set the output of the unused pin to high and pull it up to with an external resistor of approximately 100 kΩ.
Page 11 Item Page Revision (See Manual for Details) Appendix D Port Table and notes amended States in the Different Port Reset Processing States to P2 High- Table D.1 Port States impedance * Overview Notes: 1. High level output when MOS pull-up is in on state. 2.
Page 12 Rev. 6.00 Aug 04, 2006 page x of xxxvi...
Page 13: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Internal Block Diagram..................... Pin Arrangement and Functions..................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ....................... 32 Section 2 CPU ........................39 Overview........................... 39 2.1.1 Features........................ 39 2.1.2 Address Space...................... 40 2.1.3 Register Configuration..................41 Register Descriptions ......................
Page 14 2.7.3 Program Halt State....................75 2.7.4 Exception-Handling State ..................75 Memory Map ........................76 2.8.1 Memory Map ....................... 76 Application Notes ......................83 2.9.1 Notes on Data Access ..................83 2.9.2 Notes on Bit Manipulation................... 85 2.9.3 Notes on Use of the EEPMOV Instruction ............92 Section 3 Exception Handling ..................
Page 15 Section 5 Power-Down Modes ..................131 Overview........................... 131 5.1.1 System Control Registers..................134 Sleep Mode ........................138 5.2.1 Transition to Sleep Mode..................138 5.2.2 Clearing Sleep Mode.................... 139 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode..........139 Standby Mode ........................140 5.3.1 Transition to Standby Mode.................
Page 16 6.1.1 Block Diagram ..................... 156 PROM Mode (H8/3847R)....................157 6.2.1 Setting to PROM Mode ..................157 6.2.2 Socket Adapter Pin Arrangement and Memory Map........... 157 Programming (H8/3847R) ....................160 6.3.1 Writing and Verifying..................160 6.3.2 Programming Precautions ..................165 Reliability of Programmed Data ..................166 Flash Memory Overview....................
Page 17 6.11 Power-Down States for Flash Memory................200 Section 7 RAM ........................201 Overview........................... 201 7.1.1 Block Diagram ..................... 201 Section 8 I/O Ports ......................203 Overview........................... 203 Port 1..........................205 8.2.1 Overview......................205 8.2.2 Register Configuration and Description............... 205 8.2.3 Pin Functions .......................
Page 18 8.7.4 Pin States......................236 8.7.5 MOS Input Pull-Up....................237 Port 7..........................238 8.8.1 Overview......................238 8.8.2 Register Configuration and Description............... 238 8.8.3 Pin Functions ....................... 240 8.8.4 Pin States......................240 Port 8..........................241 8.9.1 Overview......................241 8.9.2 Register Configuration and Description............... 241 8.9.3 Pin Functions .......................
Page 19 9.2.3 Timer Operation....................264 9.2.4 Timer A Operation States ..................265 9.2.5 Application Note....................265 Timer C ..........................266 9.3.1 Overview......................266 9.3.2 Register Descriptions ................... 268 9.3.3 Timer Operation....................271 9.3.4 Timer C Operation States..................273 9.3.5 Usage Note......................274 Timer F..........................
Page 20 10.2.4 Operation in SSB Mode ..................343 10.2.5 Interrupt Source ....................346 10.2.6 Application Notes ....................346 10.3 SCI3 ..........................347 10.3.1 Overview......................347 10.3.2 Register Descriptions ................... 351 10.3.3 Operation ......................374 10.3.4 Interrupts......................403 10.3.5 Application Notes ....................404 Section 11 14-Bit PWM .....................
Page 21 12.5 Typical Use ........................425 12.6 Application Notes ......................428 12.6.1 Application Notes ....................428 12.6.2 Permissible Signal Source Impedance ..............429 12.6.3 Influences on Absolute Precision................. 429 Section 13 LCD Controller/Driver ................. 431 13.1 Overview........................... 431 13.1.1 Features........................ 431 13.1.2 Block Diagram .....................
Page 22 15.2.5 LCD Characteristics..................... 478 15.3 H8/3847R Group Absolute Maximum Ratings (Wide-range Specification) ....480 15.4 H8/3847R Electrical Characteristics (Wide-range Specification)........481 15.4.1 Power Supply Voltage and Operating Range............481 15.4.2 DC Characteristics ....................484 15.4.3 AC Characteristics ....................489 15.4.4 A/D Converter Characteristics ................494 15.4.5 LCD Characteristics.....................
Page 23 Block Diagrams of Port 3....................639 Block Diagrams of Port 4....................648 Block Diagram of Port 5 ....................652 Block Diagram of Port 6 ....................653 Block Diagram of Port 7 ....................654 Block Diagrams of Port 8....................655 Block Diagram of Port 9 ....................656 C.10 Block Diagram of Port A ....................
Page 24 Figures Section 1 Overview Figure 1.1 (1) Block Diagram (H8/3847R Group and H8/3847S Group) ........ Figure 1.1 (2) Block Diagram (H8/38347 Group and H8/38447 Group) ......... Figure 1.2 Pin Arrangement (FP-100B, TFP-100B and TFP-100G: Top View) ....10 Figure 1.3 Pin Arrangement (FP-100A: Top View) ............
Page 25 Figure 2.17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules ......................84 Figure 2.18 Timer Configuration Example................86 Section 3 Exception Handling Figure 3.1 Reset Sequence ....................94 Figure 3.2 Block Diagram of Interrupt Controller .............. 108 Figure 3.3 Flow Up to Interrupt Acceptance ..............
Page 26 Figure 6.4 High-Speed, High-Reliability Programming Flow Chart ........161 Figure 6.5 PROM Write/Verify Timing................164 Figure 6.6 Recommended Screening Procedure ..............166 Figure 6.7 Block Diagram of Flash Memory ..............168 Figure 6.8 Flash Memory Block Configuration ..............169 Figure 6.9 Programming/Erasing Flowchart Example in User Program Mode ....
Page 27 Figure 9.2 Block Diagram of Timer C ................267 Figure 9.3 Block Diagram of Timer F ................276 Write Access to TCR (CPU → TCF) ..............286 Figure 9.4 Read Access to TCF (TCF → CPU)..............287 Figure 9.5 Figure 9.6 TMOFH/TMOFL Output Timing..............
Page 28 Figure 10.12 Example of Operation when Transmitting in Asynchronous Mode (8-bit data, parity, 1 stop bit) ................384 Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode) ......385 Figure 10.14 Example of Operation when Receiving in Asynchronous Mode (8-bit data, parity, 1 stop bit) ................388 Figure 10.15 Data Format in Synchronous Communication...........
Page 29 Figure 13.5 LCD RAM Map with Segments Not Externally Expanded (1/4 Duty) ..... 444 Figure 13.6 LCD RAM Map with Segments Not Externally Expanded (1/3 Duty) ..... 445 Figure 13.7 LCD RAM Map with Segments Not Externally Expanded (1/2 Duty) ..... 446 Figure 13.8 LCD RAM Map with Segments Not Externally Expanded (Static Mode) ..
Page 30 Figure C.1 (d) Port 1 Block Diagram (Pin P1 )................. 633 Figure C.2 (a-1) Port 2 Block Diagram (Pins P2 to P2 , Not Including P2 in the F-ZTAT Version of the H8/38347 Group and H8/38447 Group)..........634 Figure C.2 (a-2) Port 2 Block Diagram (Pin P2 in the F-ZTAT Version of the H8/38347 Group and H8/38447 Group)..................
Page 31 Figure G.4 Chip Sectional Figure ..................673 Appendix H Form of Bonding Pads Figure H.1 Bonding Pad Form..................... 674 Figure H.2 Bonding Pad Form..................... 675 Figure H.3 Bonding Pad Form..................... 676 Appendix I Specifications of Chip Tray Figure I.1 Specifications of Chip Tray................677 Figure I.2 Specifications of Chip Tray................
Page 32 Tables Section 1 Overview Table 1.1 Features ........................Table 1.2 Bonding Pad Coordinates of H8/3847R Group (Mask ROM Version) ....13 Table 1.3 Bonding Pad Coordinates of H8/3847S Group (Mask ROM Version) ....18 Table 1.4 Bonding Pad Coordinates of HCD64F38347 and HCD64F38447......23 Table 1.5 Bonding Pad Coordinates of H8/38347 Group (Mask ROM Version) and H8/38447 Group (Mask ROM Version) ............
Page 33 Section 6 ROM Table 6.1 Setting to PROM Mode..................157 Table 6.2 Socket Adapter ....................... 157 Table 6.3 Mode Selection in PROM Mode (H8/3847R)............160 Table 6.4 DC Characteristics....................162 Table 6.5 AC Characteristics....................163 Table 6.6 Register Configuration ................... 170 Table 6.7 Division of Blocks to Be Erased ................
Page 34 Table 8.13 Port 4 Pin States ..................... 229 Table 8.14 Port 5 Registers ...................... 230 Table 8.15 Port 5 Pin Functions ....................232 Table 8.16 Port 5 Pin States ..................... 233 Table 8.17 Port 6 Registers ...................... 234 Table 8.18 Port 6 Pin Functions ....................
Page 35 Table 9.16 Input Capture Input Signal Input Edges Due to Noise Canceler Function Switching, and Conditions for Their Occurrence ..............309 Table 9.17 Watchdog Timer Registers ..................313 Table 9.18 Watchdog Timer Operation States ................. 319 Table 9.19 Pin Configuration ....................321 Table 9.20 Asynchronous Event Counter Registers ..............
Page 36 Section 13 LCD Controller/Driver Table 13.1 Pin Configuration ....................433 Table 13.2 LCD Controller/Driver Registers ................433 Table 13.3 Output Levels ......................457 Table 13.4 Power-Down Modes and Display Operation............457 Section 15 Electrical Characteristics Table 15.1 Absolute Maximum Ratings................... 463 Table 15.2 DC Characteristics....................
Page 37 Appendix A CPU Instruction Set Table A.1 Instruction Set ......................544 Table A.2 Operation Code Map ....................552 Table A.3 Number of Cycles in Each Instruction ..............554 Table A.4 Number of Cycles in Each Instruction ..............555 Appendix E List of Product Codes Table E.1 Product Code Lineup....................
Page 38 Rev. 6.00 Aug 04, 2006 page xxxvi of xxxvi...
Page 39: Section 1 Overview
Table 1.1 summarizes the features of the H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group. Notes: 1. ZTAT (Zero Turn Around Time) is a trademark of Renesas Technology Corp. 2. F-ZTAT is a trademark of Renesas Technology Corp. Rev. 6.00 Aug 04, 2006 page 1 of 680...
Page 40: Table 1.1 Features
Section 1 Overview Table 1.1 Features Item Description High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed  Max. operating speed: 8 MHz  Add/subtract: 0.25 µs (operating at 8 MHz) ...
Page 41 Section 1 Overview Item Description Power-down • Seven power-down modes modes • Sleep (high-speed) mode • Sleep (medium-speed) mode • Standby mode • Watch mode • Subsleep mode • Subactive mode • Active (medium-speed) mode Memory Large on-chip memory • H8/3842R, H8/38342, H8/38442: 16-Kbyte ROM, 1-Kbyte RAM •...
Page 42 Section 1 Overview Item Description Timers Six on-chip timers • Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (φ) * and four clock signals divided from the watch clock (φw) * •...
Page 43 Section 1 Overview Item Description A/D converter Successive approximations using a resistance ladder • 12-channel analog input pins • Conversion time: 31/φ or 62/φ per channel LCD controller/driver equipped with a maximum of 40 segment pins and four controller/driver common pins •...
Page 44 Section 1 Overview Item Description Product lineup Mask ROM ZTAT F-ZTAT ROM/RAM Version Version Version Package Size (Byte) HD6433847R HD6473847R HD64F38347 FP-100A (H8/3847R only) 60 K/2 K HD6433847S HD64F38447 FP-100B HD64338347 TFP-100B HD64338447 TFP-100G HD6433846R — — FP-100A (H8/3846R only) 48 K/2 K HD6433846S FP-100B...
Page 45: Internal Block Diagram
Section 1 Overview Internal Block Diagram Figure 1.1 (1) shows a block diagram of the H8/3847R Group and H8/3847S Group. Figure 1.1 (2) shows a block diagram of the H8/38347 Group and H8/38447 Group. /TMOW /TMOFL H8/300L /TMOFH /TMIG /COM /IRQ /ADTRG /COM...
Page 46: Figure 1.1 (2) Block Diagram (H8/38347 Group And H8/38447 Group)
Section 1 Overview /TMOW /TMOFL H8/300L /TMOFH /TMIG /COM /IRQ /ADTRG /COM /IRQ /TMIC /COM /IRQ /COM /IRQ /TMIF (60 K, 48 K, 40 K, 32 K, (2 K and 1 K) /SEG 24 K, and 16 K) /SCK /SEG /SEG /SEG Serial...
Page 47: Pin Arrangement And Functions
Section 1 Overview Pin Arrangement and Functions 1.3.1 Pin Arrangement The pin arrangements of the H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group are shown in figures 1.2 and 1.3 (figure 1.3 only applies to the H8/3847R Group). The bonding pad location diagram of the H8/3847R Group (Mask ROM version) is shown in figure 1.4.
Page 48: Figure 1.2 Pin Arrangement (Fp-100B, Tfp-100B And Tfp-100G: Top View)
Section 1 Overview /SEG /WKP /SEG /SEG /WKP /SEG /SEG /WKP /SEG /SEG /M (P9 /SEG /WKP /SEG /SEG /DO (P9 /SEG /WKP /SEG /SEG /SEG /WKP /SEG /SEG /SEG /WKP /SEG /SCK /WKP /SEG /RXD /COM /TXD /COM /IRQ /COM /COM in the H8/3847S)
Page 49: Figure 1.3 Pin Arrangement (Fp-100A: Top View)
Section 1 Overview /SEG /WKP /SEG /SEG /WKP /SEG /SEG /WKP /SEG /SEG /WKP /SEG /SEG /WKP /SEG /SCK /COM /RXD /COM /TXD /COM /IRQ /COM /AEVL /AEVH /TXD /RXD Figure 1.3 Pin Arrangement (FP-100A: Top View) Rev. 6.00 Aug 04, 2006 page 11 of 680 REJ09B0145-0600...
Page 50: Figure 1.4 Bonding Pad Location Diagram Of H8/3847R Group (Mask Rom Version) (Top View)
Section 1 Overview 98 97 96 95 94 93 92 91 90 89 88 87 86 8584 83 82 81 80 79 78 77 76 (0, 0) Type code 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 : NC Pad...
Page 51: Table 1.2 Bonding Pad Coordinates Of H8/3847R Group (Mask Rom Version)
Section 1 Overview Table 1.2 Bonding Pad Coordinates of H8/3847R Group (Mask ROM Version) Coordinates* Pad No. Pad Name X (µm) Y (µm) /TMOW -2866 1939 /TMOFL -2866 1694 /TMOFH -2866 1500 /TMIG -2866 1326 /IRQ /ADTRG -2866 /IRQ /TMIC -2866 /IRQ -2866...
Page 52 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) /AEVL -1624 -2931 -1413 -2931 -1213 -2931 -1017 -2931 -844 -2931 -672 -2931 -496 -2931 -320 -2931 /COM -112 -2931 /COM -2931 /COM -2931 /COM -2931 /WKP /SEG -2931 /WKP /SEG...
Page 53 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) /SEG 2866 /SEG 2866 /SEG 2866 /SEG 2866 /SEG 2866 /SEG 2866 /SEG 2866 1132 /SEG 2866 1318 /SEG 2866 1506 /SEG 2866 1694 /SEG 2866 1882 /SEG 2866 2070 /SEG...
Page 54 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) -1532 2931 -1704 2931 -1876 2931 -2048 2931 -2658 2931 -2866 2931 * These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The Note: home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads.
Page 55: Figure 1.5 Bonding Pad Location Diagram Of H8/3847S Group (Mask Rom Version)
Section 1 Overview 98 97 96 95 94 89 88 87 86 85 84 83 82 81 80 79 78 77 Type code (0, 0) Base type code 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 : NC Pad...
Page 56: Table 1.3 Bonding Pad Coordinates Of H8/3847S Group (Mask Rom Version)
Section 1 Overview Table 1.3 Bonding Pad Coordinates of H8/3847S Group (Mask ROM Version) Coordinates* Pad No. Pad Name X (µm) Y (µm) /TMOW -1655 1260 /TMOFL -1655 /TMOFH -1655 /TMIG -1655 /IRQ /ADTRG -1655 /IRQ /TMIC -1655 /IRQ -1655 /IRQ /TMIF -1655...
Page 57 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) /AEVL -906 -1605 -821 -1605 -736 -1605 -651 -1605 -566 -1605 -481 -1605 -396 -1605 -310 -1605 /COM -215 -1605 /COM -1605 /COM -1605 /COM -1605 /WKP /SEG -1605 /WKP /SEG...
Page 58 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) /SEG 1655 -130 /SEG 1655 /SEG 1655 /SEG 1655 /SEG 1655 /SEG 1655 /SEG 1655 /SEG 1655 /SEG 1655 /SEG 1655 /SEG 1655 /SEG 1655 1067 /SEG 1655 1527 /SEG 1466...
Page 59 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) -767 1605 -879 1605 -991 1605 -1103 1605 -1290 1605 -1523 1605 ± µ Note: * These values show the coordinates of the centers of pads. The accuracy is m.
Page 60: Figure 1.6 Bonding Pad Location Diagram Of Hcd64F38347 And Hcd64F38447 (Top View)
Section 1 Overview Type code 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 (0, 0) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 : NC Pad Chip size : 4.35mm ×...
Page 61: Table 1.4 Bonding Pad Coordinates Of Hcd64F38347 And Hcd64F38447
Section 1 Overview Table 1.4 Bonding Pad Coordinates of HCD64F38347 and HCD64F38447 Coordinates* Pad No. Pad Name X (µm) Y (µm) /TMOW -2056 1570 /TMOFL -2056 1360 /TMOFH -2056 1259 /TMIG -2056 1158 /IRQ /ADTRG -2056 /IRQ /TMIC -2056 /IRQ -2056 /IRQ /TMIF...
Page 62 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) /AEVL -1076 -2295 -896 -2295 -710 -2295 -584 -2295 -483 -2295 -382 -2295 -281 -2295 -145 -2295 /COM -2295 /COM -2295 /COM -2295 /COM -2295 /WKP /SEG1 -2295 /WKP /SEG2 -2295...
Page 63 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) /SEG20 2056 -130 /SEG21 2056 /SEG22 2056 /SEG23 2056 /SEG24 2056 /SEG25 2056 /SEG26 2056 /SEG27 2056 /SEG28 2056 1034 /SEG29 2056 1159 /SEG30 2056 1378 /SEG31 2056 1503 /SEG32 2056...
Page 64 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) -996 2295 -1102 2295 -1208 2295 -1313 2295 -1419 2295 -1530 2295 -1777 2295 Note: * These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads.
Page 65: Figure 1.7 Bonding Pad Location Diagram Of H8/38347 Group (Mask Rom Version)
Section 1 Overview Base type code 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 Type code (0, 0) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Chip size : 3.55mm ×...
Page 66: Table 1.5 Bonding Pad Coordinates Of H8/38347 Group (Mask Rom Version) And H8/38447 Group (Mask Rom Version)
Section 1 Overview Table 1.5 Bonding Pad Coordinates of H8/38347 Group (Mask ROM Version) and H8/38447 Group (Mask ROM Version) Coordinates* Pad No. Pad Name X (µm) Y (µm) /TMOW -1658 1349 /TMOFL -1658 1191 /TMOFH -1658 1104 /TMIG -1658 1006 /IRQ /ADTRG...
Page 67 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) /AEVL -907 -1767 -742 -1767 -625 -1767 -508 -1767 -416 -1767 -324 -1767 -207 -1767 -1767 /COM -1767 /COM -1767 /COM -1767 /COM -1767 /WKP /SEG1 -1767 /WKP /SEG2 -1767 /WKP...
Page 68 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) /SEG21 1658 /SEG22 1658 /SEG23 1658 /SEG24 1658 /SEG25 1658 /SEG26 1658 /SEG27 1658 /SEG28 1658 /SEG29 1658 1101 /SEG30 1658 1226 /SEG31 1658 1351 /SEG32 1658 1475 /SEG33 1658 1613...
Page 69 Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) -766 1767 -872 1767 -978 1767 -1084 1767 -1190 1767 -1629 1767 Note: * These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads.
Page 70: Pin Functions
Section 1 Overview 1.3.2 Pin Functions Table 1.6 outlines the pin functions of the H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group. Table 1.6 Pin Functions Pin No. FP-100B TFP-100B Type Symbol TFP-100G FP-100A Name and Functions Power Input Power supply: All V pins should source...
Page 71 Section 1 Overview Pin No. FP-100B TFP-100B Type Symbol TFP-100G FP-100A Name and Functions Clock pins OSC Input These pins connect to a crystal or ceramic oscillator, or can be used to Output input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram.
Page 72 Section 1 Overview Pin No. FP-100B TFP-100B Type Symbol TFP-100G FP-100A Name and Functions Timer pins TMOW Output Clock output: This is an output pin for waveforms generated by the timer A output circuit. AEVL Input Asynchronous event counter AEVH event input: This is an event input pin for input to the asynchronous event counter.
Page 73 Section 1 Overview Pin No. FP-100B TFP-100B Type Symbol TFP-100G FP-100A Name and Functions I/O ports to PA 39 to 42 42 to 45 Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA).
Page 74 Section 1 Overview Pin No. FP-100B TFP-100B Type Symbol TFP-100G FP-100A Name and Functions I/O ports to P8 74 to 67 77 to 70 Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8).
Page 75 Section 1 Overview Pin No. FP-100B TFP-100B Type Symbol TFP-100G FP-100A Name and Functions 39 to 42 42 to 45 Output LCD common output: These are controller/ the LCD common output pins. driver 82 to 43 85 to 46 Output LCD segment output: These are the LCD segment output pins.
Page 76 Section 1 Overview Rev. 6.00 Aug 04, 2006 page 38 of 680 REJ09B0145-0600...
Page 77: Section 2 Cpu
Section 2 CPU Section 2 CPU Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 78: Address Space
Section 2 CPU • Low-power operation modes SLEEP instruction for transfer to low-power operation Note: * These values are at φ = 8 MHz. 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 Kbytes for storing program code and data.
Page 79: Register Configuration
Section 2 CPU 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) SP: Stack pointer (SP) Control registers (CR) PC: Program counter 3 2 1 0 I U H U N Z V C CCR: Condition code register...
Page 80: Register Descriptions
Section 2 CPU Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
Page 81 Section 2 CPU ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling.
Page 82: Initial Register Values
Section 2 CPU 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized.
Page 83: Data Formats In General Registers
Section 2 CPU 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. Data Format Don't care 1-bit data 1-bit data Don't care Byte data Don't care Byte data...
Page 84: Memory Data Formats
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed.
Page 85: Addressing Modes
Section 2 CPU Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment...
Page 86 Section 2 CPU 4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand.
Page 87: Effective Address Calculation
Section 2 CPU The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area.
Page 88: Table 2.2 Effective Address Calculation
Section 2 CPU Table 2.2 Effective Address Calculation Rev. 6.00 Aug 04, 2006 page 50 of 680 REJ09B0145-0600...
Page 89 Section 2 CPU Rev. 6.00 Aug 04, 2006 page 51 of 680 REJ09B0145-0600...
Page 90 Section 2 CPU Rev. 6.00 Aug 04, 2006 page 52 of 680 REJ09B0145-0600...
Page 91: Instruction Set
Section 2 CPU Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Number MOV, PUSH * , POP * Data transfer Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations...
Page 92 Section 2 CPU Notation General register (destination) General register (source) General register (EAd), <Ead> Destination operand (EAs), <Eas> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 93: Data Transfer Instructions
Section 2 CPU 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 94: Figure 2.5 Data Transfer Instruction Codes
Section 2 CPU Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn→ @-Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @-SP Legend: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer Instruction Codes Rev.
Page 95: Arithmetic Operations
Section 2 CPU 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Size * Instruction Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register.
Page 96: Logic Operations
Section 2 CPU 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Size * Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 97: Shift Operations
Section 2 CPU 2.5.4 Shift Operations Table 2.7 describes the eight shift instructions. Table 2.7 Shift Instructions Size * Instruction Function Rd shift → Rd SHAL SHAR Performs an arithmetic shift operation on general register contents Rd shift → Rd SHLL SHLR Performs a logical shift operation on general register contents...
Page 98: Figure 2.6 Arithmetic, Logic, And Shift Instruction Codes
Section 2 CPU Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR...
Page 99: Bit Manipulations
Section 2 CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Size * Instruction Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 100 Section 2 CPU Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
Page 101: Figure 2.7 Bit Manipulation Instruction Codes
Section 2 CPU BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.:...
Page 102 Section 2 CPU BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Legend: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont)
Page 103: Branching Instructions
Section 2 CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function — Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition...
Page 104: Figure 2.8 Branching Instruction Codes
Section 2 CPU disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) Legend: Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes Rev. 6.00 Aug 04, 2006 page 66 of 680 REJ09B0145-0600...
Page 105: System Control Instructions
Section 2 CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Size * Instruction Function — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details.
Page 106: Block Data Transfer Instruction
Section 2 CPU RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Legend: Operation field Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size...
Page 107: Figure 2.10 Block Data Transfer Instruction Code
Section 2 CPU Legend: Operation field Figure 2.10 Block Data Transfer Instruction Code Rev. 6.00 Aug 04, 2006 page 69 of 680 REJ09B0145-0600...
Page 108: Basic Operational Timing
Section 2 CPU Basic Operational Timing CPU operation is synchronized by a system clock (φ) or a subclock (φ ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ the next rising edge is called one state.
Page 109: Access To On-Chip Peripheral Modules
Section 2 CPU 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 110: Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
Section 2 CPU Three-state access to on-chip peripheral modules Bus cycle state state state φ or φ Internal Address address bus Internal read signal Internal Read data data bus (read access) Internal write signal Internal data bus Write data (write access) Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) Rev.
Page 111: Cpu States
Section 2 CPU CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode.
Page 112: Figure 2.14 Cpu Operation States
Section 2 CPU CPU state Reset state The CPU is initialized Program Active execution state (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock...
Page 113: Program Execution State
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs occurs source handling occurs complete Program halt state Program execution state SLEEP instruction executed Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence.
Page 114: Memory Map
Section 2 CPU Memory Map 2.8.1 Memory Map The memory map of the H8/3842R, H8/38342, and H8/38442 is shown in figure 2.16 (1), that of the H8/3843R, H8/38343, and H8/38443 in figure 2.16 (2), that of the H8/3844R, H8/3844S, H8/38344, and H8/38444 in figure 2.16 (3), that of the H8/3845R, H8/3845S, H8/38345, and H8/38445 in figure 2.16 (4), that of the H8/3846R, H8/3846S, H8/38346, and H8/38446 in figure 2.16 (5), and that of the H8/3847R, H8/3847S, H8/38347, and H8/38447 in figure 2.16 (6).
Page 115: Figure 2.16 (1) H8/3842R, H8/38342 And H8/38442 Memory Map
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 16 Kbytes On-chip ROM (16384 bytes) H'3FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 On-chip RAM 1024 bytes H'FB7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (1) H8/3842R, H8/38342 and H8/38442 Memory Map Rev.
Page 116: Figure 2.16 (2) H8/3843R, H8/38343 And H8/38443 Memory Map
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 24 Kbytes On-chip ROM (24576 bytes) H'5FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 1024 bytes On-chip RAM H'FB7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (2) H8/3843R, H8/38343 and H8/38443 Memory Map Rev.
Page 117: Figure 2.16 (3) H8/3844R, H8/3844S, H8/38344 And H8/38444 Memory Map
Section 2 CPU HD6433844R (Mask ROM Version) HD6433844S (Mask ROM Version) HD64F38344 (Flash Memory Version) HD64338344 (Mask ROM Version) HD64F38444 (Flash Memory Version) HD64338444 (Mask ROM Version) H'0000 H'0000 Interrupt vector area Interrupt vector area H'0029 H'0029 H'002A H'002A 32 Kbytes 32 Kbytes (32768 bytes) (32768 bytes)
Page 118: Figure 2.16 (4) H8/3845R, H8/3845S, H8/38345 And H8/38445 Memory Map
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 40 Kbytes On-chip ROM (40960 bytes) H'9FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 2048 bytes On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (4) H8/3845R, H8/3845S, H8/38345 and H8/38445 Memory Map Rev.
Page 119: Figure 2.16 (5) H8/3846R, H8/3846S, H8/38346 And H8/38446 Memory Map
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 48 Kbytes (49152 bytes) On-chip ROM H'BFFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 2048 bytes On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (5) H8/3846R, H8/3846S, H8/38346 and H8/38446 Memory Map Rev.
Page 120: Figure 2.16 (6) H8/3847R, H8/3847S, H8/38347 And H8/38447 Memory Map
Section 2 CPU HD6433847R (Mask ROM Version) HD6433847S (Mask ROM Version) HD64338347 (Mask ROM Version) HD64F38347 (Flash Memory Version) HD64338447 (Mask ROM Version) HD64F38447 (Flash Memory Version) HD6473847R (PROM Version) H'0000 H'0000 Interrupt vector area Interrupt vector area H'0029 H'0029 H'002A H'002A On-chip ROM...
Page 121: Application Notes
Section 2 CPU Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 122: Figure 2.17 Data Size And Number Of States For Access To And From On-Chip Peripheral Modules
Section 2 CPU Access States Word Byte H'0000 Interrupt vector area (42 bytes) H'0029 H'002A 32Kbytes On-chip ROM H'7FFF Not used — — — H'F740 LCD RAM (20 bytes) H'F753 Not used — — — H'F780 On-chip RAM 2048 bytes H'FF7F Not used —...
Page 123: Notes On Bit Manipulation
Section 2 CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an I/O port.
Page 124: Figure 2.18 Timer Configuration Example
Section 2 CPU Read Count clock Timer counter Reload Write Timer load register Internal bus Figure 2.18 Timer Configuration Example Example 2: BSET instruction executed designating port 3 and P3 are designated as input pins, with a low-level signal input at P3 and a high-level signal at P3 .
Page 125 Section 2 CPU [C: After executing BSET] Input/output Input Input Output Output Output Output Output Output Pin state High High level level level level level level level level PCR3 PDR3 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3. Since P3 and P3 are input pins, the CPU reads the pin states (low-level and high-level input).
Page 126 Section 2 CPU [B: BSET instruction executed] The BSET instruction is executed designating the PDR3 BSET @RAM0 work area (RAM0). [C: After executing BSET] The work area (RAM0) value is written to PDR3. MOV. B @RAM0, MOV. B R0L, @PDR3 Input/output Input Input...
Page 127 Section 2 CPU [B: BCLR instruction executed] The BCLR instruction is executed designating PCR3. BSET @PCR3 [C: After executing BCLR] Input/output Output Output Output Output Output Output Output Input Pin state High High level level level level level level level level PCR3 PDR3...
Page 128: Table 2.12 Registers With Shared Addresses
Section 2 CPU [B: BCLR instruction executed] The BCLR instruction is executed designating the PCR3 BCLR @RAM0 work area (RAM0). [C: After executing BCLR] The work area (RAM0) value is written to PCR3. MOV. B @RAM0, MOV. B R0L, @PCR3 Input/output Input Input...
Page 129: Table 2.13 Registers With Write-Only Bits
Section 2 CPU Table 2.13 Registers with Write-Only Bits Register Name Abbr. Address Port control register 1 PCR1 H'FFE4 Port control register 2 PCR2 H'FFE5 Port control register 3 PCR3 H'FFE6 Port control register 4 PCR4 H'FFE7 Port control register 5 PCR5 H'FFE8 Port control register 6...
Page 130: Notes On Use Of The Eepmov Instruction
Section 2 CPU 2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 →...
Page 131: Section 3 Exception Handling
Section 3 Exception Handling Section 3 Exception Handling Overview Exception handling is performed in the H8/3847R Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority Exception Source Time of Start of Exception Handling...
Page 132: Interrupt Immediately After Reset
Section 3 Exception Handling When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. Reset cleared Program initial instruction prefetch Vector fetch Internal processing φ Internal address bus Internal read...
Page 133: Interrupts
Section 3 Exception Handling Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (IRQ to IRQ , WKP to WKP ) and 24 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed.
Page 134: Table 3.2 Interrupt Sources And Their Priorities
Section 3 Exception Handling Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt Vector Number Vector Address Priority Reset H'0000 to H'0001 High Watchdog timer H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 SCI1 SCI1 transfer complete...
Page 135: Interrupt Control Registers
Section 3 Exception Handling 3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Abbreviation Initial Value Address IRQ edge select register IEGR H'E0 H'FFF2 Interrupt enable register 1 IENR1 H'00 H'FFF3 Interrupt enable register 2 IENR2 H'00...
Page 136 Section 3 Exception Handling Bit 3: IRQ edge select (IEG3) Bit 3 selects the input sensing of the IRQ pin and TMIF pin. Bit 3 IEG3 Description Falling edge of IRQ and TMIF pin input is detected (initial value) Rising edge of IRQ and TMIF pin input is detected Bit 2: IRQ edge select (IEG2)
Page 137 Section 3 Exception Handling 2. Interrupt Enable Register 1 (IENR1) IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests.
Page 138 Section 3 Exception Handling Bits 4 to 0: IRQ to IRQ interrupt enable (IEN4 to IEN0) Bits 4 to 0 enable or disable IRQ to IRQ interrupt requests. Bit n IENn Description Disables interrupt requests from pin IRQn (initial value) Enables interrupt requests from pin IRQn (n = 4 to 0) 3.
Page 139 Section 3 Exception Handling Bit 4: Timer G interrupt enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests. Bit 4 IENTG Description Disables timer G interrupt requests (initial value) Enables timer G interrupt requests Bit 3: Timer FH interrupt enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Page 140 Section 3 Exception Handling Bit 0: Asynchronous event counter interrupt enable (IENEC) Bit 0 enables or disables asynchronous event counter interrupt requests. Bit 0 IENEC Description Disables asynchronous event counter interrupt requests (initial value) Enables asynchronous event counter interrupt requests For details of SCI3-1 and SCI3-2 interrupt control, see 6.
Page 141 Section 3 Exception Handling Bit 6: SCI1 interrupt request flag (IRRS1) Bit 6 IRRS1 Description Clearing condition: (initial value) When IRRS1 = 1, it is cleared by writing 0 Setting condition: When SCI1 completes transfer Bit 5: Reserved bit Bit 5 is reserved; it is always read as 1 and cannot be modified. Bits 4 to 0: IRQ to IRQ interrupt request flags (IRRI4 to IRRI0)
Page 142 Section 3 Exception Handling Bit 7: Direct transfer interrupt request flag (IRRDT) Bit 7 IRRDT Description Clearing condition: (initial value) When IRRDT = 1, it is cleared by writing 0 Setting condition: When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in SYSCR2 Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6...
Page 143 Section 3 Exception Handling Bit 3: Timer FH interrupt request flag (IRRTFH) Bit 3 IRRTFH Description Clearing condition: (initial value) When IRRTFH = 1, it is cleared by writing 0 Setting condition: When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH) match in 16-bit timer mode Bit 2: Timer FL interrupt request flag (IRRTFL) Bit 2...
Page 144 Section 3 Exception Handling 6. Wakeup Interrupt Request Register (IWPR) IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Note: * All bits can only be written with 0, for flag clearing. IWPR is an 8-bit read/write register containing wakeup interrupt request flags.
Page 145: External Interrupts
Section 3 Exception Handling Bit n: WKPn edge select (WKEGSn) Bit n selects WKPn pin input sensing. Bit n WKEGSn Description WKPn pin falling edge detected (initial value) WKPn pin rising edge detected (n = 7 to 0) 3.3.3 External Interrupts There are 13 external interrupts: IRQ to IRQ and WKP...
Page 146: Internal Interrupts
Section 3 Exception Handling 3.3.4 Internal Interrupts There are 24 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2.
Page 147 Section 3 Exception Handling Interrupt operation is described as follows. • When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. • When the interrupt controller receives an interrupt request, it sets the interrupt request flag. •...
Page 148: Figure 3.3 Flow Up To Interrupt Acceptance
Section 3 Exception Handling Program execution state IRRI0 = 1 IEN0 = 1 IRRI1 = 1 IEN1 = 1 IRRI2 = 1 IEN2 = 1 IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ←...
Page 149: Figure 3.4 Stack State After Completion Of Interrupt Exception Handling
Section 3 Exception Handling SP – 4 SP (R7) SP – 3 SP + 1 SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling...
Page 150: Figure 3.5 Interrupt Sequence
Section 3 Exception Handling Figure 3.5 Interrupt Sequence Rev. 6.00 Aug 04, 2006 page 112 of 680 REJ09B0145-0600...
Page 151: Interrupt Response Time
Section 3 Exception Handling 3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction * 1 to 13...
Page 152: Application Notes
Section 3 Exception Handling Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3847R Group, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 153: Notes On Rewriting Port Mode Registers
Section 3 Exception Handling 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ to IRQ , WKP...
Page 154: Table 3.5 Conditions Under Which Interrupt Request Flag Is Set To 1
Section 3 Exception Handling Table 3.5 Conditions Under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 Conditions When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ IRR1 IRRI4 is low and IEGR bit IEG4 = 0.
Page 155: Figure 3.7 Port Mode Register Setting And Interrupt Request Flag Clearing Procedure
Section 3 Exception Handling An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. Interrupts masked. (Another possibility is to disable the relevant interrupt in CCR I bit←1 interrupt enable register 1.)
Page 156: Method For Clearing Interrupt Request Flags
Section 3 Exception Handling 3.4.3 Method for Clearing Interrupt Request Flags Use the recommended method, given below when clearing the flags of interrupt request registers (IRR1, IRR2, IWPR). • Recommended method Use a single instruction to clear flags. The bit control instruction and byte-size data transfer instruction can be used.
Page 157: Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators Section 4 Clock Pulse Generators Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 158: System Clock Generator
Section 4 Clock Pulse Generators System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. Connecting a Crystal Oscillator Figure 4.2 shows a typical method of connecting a crystal oscillator. For information on recommended resonators, see the product AC characteristics listed in section 15, Electrical Characteristics.
Page 159: Figure 4.4 Board Design Of Oscillator Circuit
Section 4 Clock Pulse Generators Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4.4.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC and OSC To be avoided...
Page 160: Subclock Generator
Section 4 Clock Pulse Generators The circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board. When using the oscillator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. Subclock Generator 1.
Page 161: Figure 4.8 Pin Connection When Not Using Subclock
Section 4 Clock Pulse Generators 2. Pin Connection when Not Using Subclock When the subclock is not used, connect pin X to GND and leave pin X open, as shown in figure 4.8. Open Figure 4.8 Pin Connection when not Using Subclock 3.
Page 162: Figure 4.9 (B) Pin Connection When Inputting External Clock (H8/38347 Group And H8/38447 Group)
Section 4 Clock Pulse Generators • H8/38347 Group and H8/38447 Group Connect pin X to GND and leave pin X open. Input an external clock to pin EXCL. Set bit EXCL in register PMR2 to 1 to supply the external clock to the internal components of the device. A connection example is shown in figure 4.9 (b).
Page 163: Prescalers
Section 4 Clock Pulse Generators Prescalers The H8/3847R Group is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (φ...
Page 164: Note On Oscillators
Section 4 Clock Pulse Generators Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM, ZTAT™ and F-ZTAT™ versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors.
Page 165: Definition Of Oscillation Stabilization Wait Time
Section 4 Clock Pulse Generators Modification point OSC1 OSC1 OSC2 OSC2 Negative resistance, addition of −R (1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1 Modification point Modification point OSC1 OSC1 OSC2 OSC2 (3) Oscillator Circuit Modification Suggestion 2 (4) Oscillator Circuit Modification Suggestion 3 Figure 4.11 Negative Resistance Measurement and Circuit Modification Suggestions 4.5.1...
Page 166: Figure 4.12 Oscillation Stabilization Wait Time
Section 4 Clock Pulse Generators 1. Oscillation Stabilization Time (t The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes.
Page 167: Notes On Use Of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
Section 4 Clock Pulse Generators amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is, the oscillation stabilization time—is required. The oscillation stabilization time in the case of these state transitions is the same as the oscillation stabilization time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time t rc "...
Page 168 Section 4 Clock Pulse Generators If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES pin low for a longer period. Rev. 6.00 Aug 04, 2006 page 130 of 680 REJ09B0145-0600...
Page 169: Section 5 Power-Down Modes
Section 5 Power-Down Modes Section 5 Power-Down Modes Overview This LSI has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating modes.
Page 170: Figure 5.1 Mode Transition Diagram
Section 5 Power-Down Modes Program Program Reset state execution state halt state SLEEP instruction Active Sleep (high-speed) (high-speed) Program mode mode halt state Standby mode SLEEP instruction Active Sleep (medium-speed) (medium-speed) mode mode SLEEP SLEEP instruction instruction Watch Subactive Subsleep mode mode mode...
Page 171: Table 5.2 Internal State In Each Operating Mode
Section 5 Power-Down Modes Table 5.2 Internal State in Each Operating Mode Active Mode Sleep Mode High- Medium- High- Medium- Watch Subactive Subsleep Standby Function Speed Speed Speed Speed Mode Mode Mode Mode System clock oscillator Functions Functions Functions Functions Halted Halted Halted...
Page 172: System Control Registers
Section 5 Power-Down Modes 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Registers Name Abbreviation Initial Value Address System control register 1 SYSCR1 H'07 H'FFF0 System control register 2 SYSCR2 H'F0 H'FFF1...
Page 173 Section 5 Power-Down Modes Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time.
Page 174 Section 5 Power-Down Modes Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0) Bits 1 and 0 choose φ /128, φ /64, φ /32, or φ /16 as the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-speed) mode or subactive mode.
Page 175 Section 5 Power-Down Modes Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits.
Page 176: Sleep Mode
Section 5 Power-Down Modes Bits 1 and 0: Subactive mode clock select (SA1 and SA0) /2, φ /4, or φ These bits select the CPU clock rate (φ /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 Bit 0 Description...
Page 177: Clearing Sleep Mode
Section 5 Power-Down Modes 5.2.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous counter, , SCI1, SCI3-1, SCI3-2, or A/D converter), or by input at the RES to IRQ , WKP to WKP pin.
Page 178: Standby Mode
Section 5 Power-Down Modes Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0.
Page 179: Standby Mode Transition And Pin States
Section 5 Power-Down Modes Table 5.4 Clock Frequency and Settling Time (Times are in ms) STS2 STS1 STS0 Waiting Time 2 MHz 1 MHz 8,192 states 16,384 states 16.4 32,768 states 16.4 32.8 65,536 states 32.8 65.5 131,072 states 65.5 131.1 2 states (not available) 0.001...
Page 180: Notes On External Input Signal Changes Before/After Standby Mode
Section 5 Power-Down Modes 5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ or WKP is input, both the high- and low-level widths of the signal must be at least two cycles of system clock φ...
Page 181: Figure 5.3 External Input Signal Capture When Signal Changes Before/After
Section 5 Power-Down Modes Active (high-speed, Wait for Active (high-speed, Operating medium-speed) mode Standby mode oscillation medium-speed) mode mode or subactive mode or watch mode to settle or subactive mode subcyc subcyc subcyc subcyc φ or φ External input signal Capture possible: case 1 Capture possible:...
Page 182: Watch Mode
Section 5 Power-Down Modes Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F, timer G, AEC, and the LCD controller/driver (for which operation or halting can be set) is halted.
Page 183: Subsleep Mode
Section 5 Power-Down Modes Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1.
Page 184: Subactive Mode
Section 5 Power-Down Modes Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ , or WKP WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous counter, SCI1, SCI3-1, SCI3-2, IRQ to IRQ...
Page 185: Active (Medium-Speed) Mode
Section 5 Power-Down Modes Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ , IRQ , or WKP...
Page 186: Direct Transfer
Section 5 Power-Down Modes Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution.
Page 187: Direct Transition Times
Section 5 Power-Down Modes • Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
Page 188 Section 5 Power-Down Modes 2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
Page 189: Notes On External Input Signal Changes Before/After Direct Transition
Section 5 Power-Down Modes 4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA.
Page 190: Module Standby Mode
Section 5 Power-Down Modes Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts.
Page 191: Table 5.5 Setting And Clearing Module Standby Mode By Clock Stop Register
Section 5 Power-Down Modes Table 5.5 Setting and Clearing Module Standby Mode by Clock Stop Register Register Name Bit Name Operation CKSTPR1 TACKSTP 1 Timer A module standby mode is cleared 0 Timer A is set to module standby mode TCCKSTP 1 Timer C module standby mode is cleared 0 Timer C is set to module standby mode...
Page 192: Usage Note
Section 5 Power-Down Modes 5.9.3 Usage Note If, due to the timing with which a peripheral module issues interrupt requests, the module in question is set to module standby mode before an interrupt is processed, the module will stop with the interrupt request still pending.
Page 193: Section 6 Rom
Section 6 ROM Section 6 ROM Overview The H8/3842R, H8/38342, and H8/38442 have 16 Kbytes of mask ROM, the H8/3843R, H8/38343, and H8/38443 have 24 Kbytes of mask ROM, the H8/3844R, H8/3844S, H8/38344, and H8/38444 have 32 Kbytes of mask ROM, the H8/3845R, H8/3845S, H8/38345, and H8/38445 have 40 Kbytes of mask ROM, the H8/3846R, H8/3846S, H8/38346, and H8/38446 have 48 Kbytes of mask ROM, and the H8/3847R, H8/3847S, H8/38347, and H8/38447 have 60 Kbytes of mask ROM on-chip.
Page 194: Block Diagram
Section 6 ROM 6.1.1 Block Diagram Figure 6.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0000 H'0001 H'0002 H'0002 H'0003 On-chip ROM H'7FFE H'7FFE H'7FFF Even-numbered Odd-numbered address address...
Page 195: Prom Mode (H8/3847R)
Section 6 ROM PROM Mode (H8/3847R) 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM.
Page 196: Figure 6.2 Socket Adapter Pin Correspondence (With Hn27C101)
Section 6 ROM H8/3847R EPROM socket FP-100B, HN27C101 FP-100A TFP-100B (32-pin) 38, 32 41, 35 , CV TEST 11, 33 14, 36 Note: Pins not indicated in the figure should be left open. Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101) Rev.
Page 197: Figure 6.3 H8/3847R Memory Map In Prom Mode
Section 6 ROM Address in Address in MCU mode PROM mode H'0000 H'0000 On-chip PROM H'EDFF H'EDFF Uninstalled area* H'1FFFF Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF.
Page 198: Programming (H8/3847R)
Section 6 ROM Programming (H8/3847R) The write, verify, and other modes are selected as shown in table 6.3 in PROM mode. (H8/3847R) Table 6.3 Mode Selection in PROM Mode (H8/3847R) Pins Mode to EO to EA Write Data input Address input Verify Data output Address input...
Page 199: Figure 6.4 High-Speed, High-Reliability Programming Flow Chart
Section 6 ROM Start Set write/verify mode = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V Address = 0 n = 0 → n + 1 < n 25 Write time t = 0.2 ms ± 5% No Go →...
Page 200: Table 6.4 Dc Characteristics
Section 6 ROM Tables 6.4 and 6.5 give the electrical characteristics in programming mode. Table 6.4 DC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Test Condition...
Page 201: Table 6.5 Ac Characteristics
Section 6 ROM Table 6.5 AC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C) Item Symbol Min Typ Unit Test Condition Figure 6.5 * Address setup time — — µs OE setup time —...
Page 202: Figure 6.5 Prom Write/Verify Timing
Section 6 ROM Figure 6.5 shows a PROM write/verify timing diagram. Write Verify Address Data Input data Output data CC +1 Note: * t is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart. Figure 6.5 PROM Write/Verify Timing Rev.
Page 203: Programming Precautions
) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. • Setting the PROM programmer to Renesas specifications for the HN27C101 will result in correct V of 12.5 V.
Page 204: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas Technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 205: Flash Memory Overview
Section 6 ROM Flash Memory Overview 6.5.1 Features The features of the 60 Kbytes or 32 Kbytes of flash memory built into the F-ZTAT versions are summarized below. • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 206: Block Diagram
Section 6 ROM 6.5.2 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 TES pin FLMCR2 Operating Bus interface/controller P24 pin mode P26 pin FLPWCR FENR Flash memory Legend: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR: Erase block register FLPWCR: Flash memory power control register...
Page 207: Figure 6.8 Flash Memory Block Configuration
Section 6 ROM H'0000 H'0001 H'0002 Programming unit: 128 bytes H'007F H'0080 H'0081 H'0082 H'00FF Erase unit 1 Kbyte H'0380 H'0381 H'0382 H'03FF H'0400 H'0401 H'0402 Programming unit: 128 bytes H'047F H'0480 H'0481 H'0482 H'04FF Erase unit 1 Kbyte H'0780 H'0781 H'0782 H'07FF...
Page 208: Register Configuration
Section 6 ROM 6.5.4 Register Configuration Table 6.6 lists the register configuration to control the flash memory when the built in flash memory is effective. Table 6.6 Register Configuration Register Name Abbreviation Initial Value Address Flash memory control register 1 FLMCR1 H'00 H'F020...
Page 209: Descriptions Of Registers Of The Flash Memory
Section 6 ROM Descriptions of Registers of the Flash Memory 6.6.1 Flash Memory Control Register 1 (FLMCR1) — Initial value Read/Write — FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash Memory Programming/Erasing.
Page 210 Section 6 ROM Bit 5—Erase Setup (ESU) This bit is to prepare for changing to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1 (do not set SWE, PSU, EV, PV, E, and P bits at the same time). Bit 5 Description The erase setup state is cancelled...
Page 211 Section 6 ROM Bit 2—Program-Verify (PV) This bit is to set changing to or cancelling program-verify mode (do not set SWE, ESU, PSU, EV, E, and P bits at the same time). Bit 2 Description Program-verify mode is cancelled (initial value) The flash memory changes to program-verify mode Bit 1—Erase (E) This bit is to set changing to or cancelling erase mode (do not set SWE, ESU, PSU, EV, PV, and P...
Page 212: Flash Memory Control Register 2 (Flmcr2)
Section 6 ROM 6.6.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — — — Initial value Read/Write — — — — — — — FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Page 213: Flash Memory Power Control Register (Flpwcr)
Section 6 ROM Table 6.7 Division of Blocks to Be Erased Bit Name Block (Size) Address EB0 (1 Kbyte) H'0000 to H'03FF EB1 (1 Kbyte) H'0400 to H'07FF EB2 (1 Kbyte) H'0800 to H'0BFF EB3 (1 Kbyte) H'0C00 to H'0FFF EB4 (28 Kbytes) H'1000 to H'7FFF EB5 (16 Kbyte)
Page 214: Flash Memory Enable Register (Fenr)
Section 6 ROM 6.6.5 Flash Memory Enable Register (FENR) FLSHE — — — — — — — Initial value Read/Write — — — — — — — FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and FLPWCR.
Page 215: On-Board Programming Modes
Section 6 ROM On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode.
Page 216: Boot Mode
Section 6 ROM 6.7.1 Boot Mode Table 6.9 shows the boot mode operations between reset end and branching to the programming control program. The device uses SCI32 in the boot mode. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand.
Page 217: Table 6.9 Boot Mode Operation
Section 6 ROM 8. Do not change the TEST pin and P24 pin input levels in boot mode. Table 6.9 Boot Mode Operation Host Operation LSI Operation Processing Contents Processing Contents Item Branches to boot program at reset-start. Bit rate Continuously transmits data H'00 at ·...
Page 218: Programming/Erasing In User Program Mode
Section 6 ROM 6.7.2 Programming/Erasing in User Program Mode The term user mode refers to the status when a user program is being executed. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data.
Page 219: Program/Program-Verify
Section 6 ROM program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 6.8.1, Program/Program-Verify and section 6.8.2, Erase/Erase-Verify, respectively. 6.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 6.10 should be followed.
Page 220: Figure 6.10 Program/Program-Verify Flowchart
Section 6 ROM Write pulse application subroutine Apply Write Pulse START Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 128-byte program data in program data area and reprogram data area Wait 50 µs n = 1 Set P bit in FLMCR1 m = 0...
Page 221: Table 6.11 Reprogram Data Computation Table
Section 6 ROM Table 6.11 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments Programming completed Reprogram bit — Remains in erased state Table 6.12 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming...
Page 222: Erase/Erase-Verify
Section 6 ROM 6.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR).
Page 223: Figure 6.11 Erase/Erase-Verify Flowchart
Section 6 ROM Erase start SWE bit ← 1 Wait 1 µs n ← 1 Set EBR Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ←...
Page 224: Program/Erase Protection
Section 6 ROM Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode.
Page 225: Programmer Mode
Use a PROM programmer that supports the MCU device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-Kbyte flash memory (F-ZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to programmer mode, see table 6.8.
Page 226: Table 6.14 Command Sequence In Programmer Mode
Section 6 ROM Table 6.14 Command Sequence in Programmer Mode 1st Cycle 2nd Cycle Number of Cycles Command Name Mode Address Data Mode Address Data Memory read 1 + n Write H'00 Read Dout Auto-program Write H'40 Write Auto-erase Write H'20 Write H'20...
Page 227: Figure 6.12 Socket Adapter Pin Correspondence Diagram
Section 6 ROM F-ZTAT Device Pin Name Socket Adapter Pin No. HN28F101 (32 Pins) (Conversion to FP-100B 32-Pin TFP-100B Pin Name Pin No. Arrangement) TFP-100G I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 32, 38 CVcc, Vcc AVcc TEST Legend: FWE: Flash-write enable I/O7 to I/O0: Data input/output...
Page 228: Memory Read Mode
Section 6 ROM 6.10.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. Once memory read mode has been entered, consecutive reads can be performed.
Page 229: Figure 6.13 Timing Waveforms For Memory Read After Memory Write
Section 6 ROM Command write Memory read mode Address stable A15−A0 nxtc I/O7−I/O0 Note: Data is latched on the rising edge of WE. Figure 6.13 Timing Waveforms for Memory Read after Memory Write Table 6.16 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T...
Page 230: Figure 6.14 Timing Waveforms In Transition From Memory Read Mode To Another Mode
Section 6 ROM Memory read mode Other mode command write Address stable A15−A0 nxtc I/O7−I/O0 Note: Do not enable WE and OE at the same time. Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 6.17 AC Characteristics in Memory Read Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T...
Page 231: Auto-Program Mode
Section 6 ROM Address stable Address stable A15−A0 I/O7−I/O0 Figure 6.16 CE CE and OE OE Clock System Read Timing Waveforms 6.10.4 Auto-Program Mode 1. When reprogramming previously programmed addresses, perform auto-erasing before auto- programming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed.
Page 232: Figure 6.17 Auto-Program Mode Timing Waveforms
Section 6 ROM Table 6.18 AC Characteristics in Auto-Program Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs Figure 6.17 nxtc CE hold time —...
Page 233: Auto-Erase Mode
Section 6 ROM 6.10.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4.
Page 234: Status Read Mode
Section 6 ROM A15−A0 nxtc nxtc ests erase I/O7 Erase end decision signal I/O6 Erase normal decision signal I/O5−I/O0 H'20 H'20 H'00 Figure 6.18 Auto-Erase Mode Timing Waveforms 6.10.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Page 235: Figure 6.19 Status Read Mode Timing Waveforms
Section 6 ROM Table 6.20 AC Characteristics in Status Read Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Read time after command write — µs Figure 6.19 nxtc CE hold time —...
Page 236: Status Polling
Section 6 ROM Table 6.21 Status Read Mode Return Codes Pin Name Initial Value Indications I/O7 1: Abnormal end 0: Normal end I/O6 1: Command error 0: Otherwise I/O5 1: Programming error 0: Otherwise I/O4 1: Erasing error 0: Otherwise ...
Page 237: Programmer Mode Transition Time
2. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.
Page 238: Power-Down States For Flash Memory
Section 6 ROM 6.11 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: • Normal operating mode The flash memory can be read and written to at high speed. • Power-down operating mode The power supply circuit of the flash memory is partly halted and can be read under low power consumption.
Page 239: Section 7 Ram
Section 7 RAM Section 7 RAM Overview The H8/3842R, H8/3843R, H8/38342, H8/38343, H8/38442, and H8/38443 have 1 Kbytes of high-speed static RAM, and H8/3844R, H8/3844S, H8/38344, H8/38444, H8/3845R, H8/3845S, H8/38345, H8/38445, H8/3846R, H8/3846S, H8/38346, H8/38446, H8/3847R, H8/3847S, H8/38347, and H8/38447 have 2 Kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
Page 240 Section 7 RAM Rev. 6.00 Aug 04, 2006 page 202 of 680 REJ09B0145-0600...
Page 241: Section 8 I/O Ports
Section 8 I/O Ports Section 8 I/O Ports Overview The H8/3847R Group, H8/3847S Group and H8/38347 Group are provided with eight 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port, one 8-bit input-only port, one 4-bit input-only port, and one 1-bit input-only port.
Page 242 Section 8 I/O Ports Function Switching Port Description Pins Other Functions Registers Port 3 • 8-bit I/O port /AEVL SCI3-1 data output (TXD ), data PMR3 /AEVH input (RXD ), clock input/output SCR31 • MOS input pull-up /TXD (SCK ), and asynchronous counter SMR31 option /RXD...
Page 243: Port 1
Section 8 I/O Ports Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Figure 8.1 shows its pin configuration. P1 /IRQ /TMIF P1 /IRQ P1 /IRQ /TMIC P1 /IRQ /ADTRG Port 1 P1 /TMIG P1 /TMOFH P1 /TMOFL P1 /TMOW Figure 8.1 Port 1 Pin Configuration 8.2.2...
Page 244 Section 8 I/O Ports 1. Port Data Register 1 (PDR1) Initial value Read/Write PDR1 is an 8-bit register that stores data for port 1 pins P1 to P1 . If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Page 245 Section 8 I/O Ports 4. Port Mode Register 1 (PMR1) IRQ3 IRQ2 IRQ1 IRQ4 TMIG TMOFH TMOFL TMOW Initial value Read/Write PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7: P1 /IRQ /TMIF pin function switch (IRQ3)
Page 246 Section 8 I/O Ports Bit 5: P1 /IRQ /TMIC pin function switch (IRQ1) /TMIC is used as P15 or as IRQ This bit selects whether pin P1 /IRQ /TMIC. Bit 5 IRQ1 Description Functions as P1 I/O pin (initial value) Functions as IRQ /TMIC input pin Note: Rising or falling edge sensing can be designated for IRQ...
Page 247 Section 8 I/O Ports Bit 1: P1 /TMOFL pin function switch (TMOFL) This bit selects whether pin P1 /TMOFL is used as P1 or as TMOFL. Bit 1 TMOFL Description Functions as P1 I/O pin (initial value) Functions as TMOFL output pin Bit 0: P1 /TMOW pin function switch (TMOW) This bit selects whether pin P1...
Page 248: Pin Functions
Section 8 I/O Ports 8.2.3 Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Functions and Selection Method /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 in PCR1.
Page 249: Pin States
Section 8 I/O Ports Pin Functions and Selection Method /TMIG The pin function depends on bit TMIG in PMR1 and bit PCR1 in PCR1. TMIG PCR1 Pin function input pin output pin TMIG input pin /TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR1 in PCR1.
Page 250: Mos Input Pull-Up
Section 8 I/O Ports 8.2.5 MOS Input Pull-Up Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin.
Page 251: Port 2
Section 8 I/O Ports Port 2 8.3.1 Overview Port 2 is an 8-bit I/O port. Figure 8.2 shows its pin configuration. In the F-ZTAT version, the on-chip pull-up MOS for pin P2 is on during the reset period. It turns off and normal operation resumes after the reset is cleared.
Page 252 Section 8 I/O Ports 1. Port Data Register 2 (PDR2) Initial value Read/Write PDR2 is an 8-bit register that stores data for port 2 pins P2 to P2 . If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read.
Page 253 Section 8 I/O Ports • H8/38347 Group and H8/38447 Group EXCL — POF1 — — SCK1 Initial value Read/Write — — — PMR2 is an 8-bit read/write register that controls the selection of pin functions for pins P2 , P2 and P2 , the PMOS on/off state for the P2 pin, and external clock input to pin P31.
Page 254 Section 8 I/O Ports Bit 2: P2 pin function switch (SO1) This bit selects whether pin P2 is used as P2 or as SO Bit 2 Description Functions as P2 I/O pin (initial value) Functions as SO output pin Bit 1: P2 pin function switch (SI1) This bit selects whether pin P2 is used as P2...
Page 255: Pin Function
Section 8 I/O Ports Bit n: NMOS open-drain output select (NMODn) These bits select NMOS open-drain output when pin P2 is used as an output pin. Bit n NMODn Description CMOS output (initial value) NMOS open-drain output (n = 7 to 0) 8.3.3 Pin Function Table 8.6 shows the port 2 pin functions.
Page 256: Pin States
Section 8 I/O Ports 8.3.4 Pin States Table 8.7 shows the port 2 pin states in each operating mode. Table 8.7 Port 2 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active to P2 High- Retains Retains High- Retains Functional Functional impedance...
Page 257: Port 3
Section 8 I/O Ports Port 3 8.4.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8.3. P3 /AEVL P3 /AEVH P3 /TXD P3 /RXD Port 3 P3 /SCK P3 /RESO* P3 /UD/EXCL* P3 /PWM Notes: 1. The RESO function is not implemented in the H8/38347 Group and H8/38447 Group. 2.
Page 258 Section 8 I/O Ports 1. Port Data Register 3 (PDR3) Initial value Read/Write PDR3 is an 8-bit register that stores data for port 3 pins P3 to P3 . If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Page 259 Section 8 I/O Ports 4. Port Mode Register 3 (PMR3) AEVL AEVH WDCKS IRQ0 RESO* Initial value Read/Write PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'04. Note: * The RESO bit is not implemented in the H8/38347 Group and H8/38447 Group.
Page 260 Section 8 I/O Ports Bit 4: TMIG noise canceler select (NCS) This bit controls the noise canceler for the input capture input signal (TMIG). Bit 4 Description Noise cancellation function not used (initial value) Noise cancellation function used Bit 3: P4 /IRQ pin function switch (IRQ0) or as IRQ...
Page 261: Pin Functions
Section 8 I/O Ports In the H8/38347 Group and H8/38447 Group this pin is a combined P31/UD/EXCL pin. Refer to the description of port mode register 2 in 8.3, Port 2, for details on switching to the EXCL pin function. Bit 0: P3 /PWM pin function switch (PWM) This bit selects whether pin P3...
Page 262 Section 8 I/O Ports Pin Functions and Selection Method /SCK The pin function depends on bits CKE1, CKE0, and SMR31 in SCR3-1 and bit PCR3 in PCR3. CKE1 CKE0 COM3 PCR3 Pin function input pin P3 output pin output pin input pin /RESO •...
Page 263: Pin States
Section 8 I/O Ports 8.4.4 Pin States Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /AEVL High- Retains Retains High- Retains Functional Functional impedance * /AEVH...
Page 264: Port 4
Section 8 I/O Ports Port 4 8.5.1 Overview Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.4. /IRQ /TXD Port 4 /RXD /SCK Figure 8.4 Port 4 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 4 register configuration.
Page 265 Section 8 I/O Ports 2. Port Control Register 4 (PCR4) — — — — — PCR4 PCR4 PCR4 Initial value Read/Write — — — — — PCR4 is an 8-bit register for controlling whether each of port 4 pins P4 to P4 functions as an input pin or output pin.
Page 266: Pin Functions
Section 8 I/O Ports 8.5.3 Pin Functions Table 8.12 shows the port 4 pin functions. Table 8.12 Port 4 Pin Functions Pin Functions and Selection Method /IRQ The pin function depends on bit IRQ0 in PMR3. IRQ0 Pin function input pin input pin /TXD The pin function depends on bit TE in SCR3-2, bit SPC32 in SPCR, and bit...
Page 267: Pin States
Section 8 I/O Ports 8.5.4 Pin States Table 8.13 shows the port 4 pin states in each operating mode. Table 8.13 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ High- Retains Retains High- Retains Functional Functional /TXD impedance...
Page 268: Port 5
Section 8 I/O Ports Port 5 8.6.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.5. /WKP /SEG /WKP /SEG /WKP /SEG /WKP /SEG Port 5 /WKP /SEG /WKP /SEG /WKP /SEG /WKP /SEG Figure 8.5 Port 5 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 5 register configuration.
Page 269 Section 8 I/O Ports 1. Port Data Register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 270: Pin Functions
Section 8 I/O Ports Upon reset, PUCR5 is initialized to H'00. 4. Port Mode Register 5 (PMR5) Initial value Read/Write PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n: P5 /WKP /SEG...
Page 271: Pin States
Section 8 I/O Ports 8.6.4 Pin States Table 8.16 shows the port 5 pin states in each operating mode. Table 8.16 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /WKP High- Retains Retains High- Retains Functional Functional to P5 impedance...
Page 272: Port 6
Section 8 I/O Ports Port 6 8.7.1 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.6. /SEG /SEG /SEG /SEG Port 6 /SEG /SEG /SEG /SEG Figure 8.6 Port 6 Pin Configuration 8.7.2 Register Configuration and Description Table 8.17 shows the port 6 register configuration.
Page 273 Section 8 I/O Ports 1. Port Data Register 6 (PDR6) Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states.
Page 274: Pin Functions
Section 8 I/O Ports 3. Port Pull-Up Control Register 6 (PUCR6) PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 Initial value Read/Write PUCR6 controls whether the MOS pull-up of each of the port 6 pins P6 to P6 is on or off. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 275: Mos Input Pull-Up
Section 8 I/O Ports 8.7.5 MOS Input Pull-Up Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset.
Page 276: Overview
Section 8 I/O Ports Port 7 8.8.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8.7. /SEG /SEG /SEG /SEG Port 7 /SEG /SEG /SEG /SEG Figure 8.7 Port 7 Pin Configuration 8.8.2 Register Configuration and Description Table 8.20 shows the port 7 register configuration.
Page 277 Section 8 I/O Ports 1. Port Data Register 7 (PDR7) Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 . If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Page 278: Pin Functions
Section 8 I/O Ports 8.8.3 Pin Functions Table 8.21 shows the port 7 pin functions. Table 8.21 Port 7 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR7 in PCR7 and bits SGS3 to SGS0 in to P7 /SEG LPCR.
Page 279: Overview
Section 8 I/O Ports Port 8 8.9.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8.8. /SEG /SEG /SEG /SEG Port 8 /SEG /SEG /SEG /SEG Figure 8.8 Port 8 Pin Configuration 8.9.2 Register Configuration and Description Table 8.23 shows the port 8 register configuration.
Page 280 Section 8 I/O Ports 1. Port Data Register 8 (PDR8) Initial value Read/Write PDR8 is an 8-bit register that stores data for port 8 pins P8 to P8 . If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Page 281: Pin Functions
Section 8 I/O Ports 8.9.3 Pin Functions Table 8.24 shows the port 8 pin functions. Table 8.24 Port 8 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR8 in PCR8 and bits SGS3 to SGS0 in to P8 /SEG LPCR.
Page 282: Port 9
Section 8 I/O Ports 8.10 Port 9 8.10.1 Overview Port 9 is an 8-bit I/O port. Figure 8.9 shows its pin configuration. /SEG /SEG /DO * /SEG /M * /SEG Port 9 /SEG /SEG /SEG /SEG Note: * The CL , CL , DO, and M functions are not implemented on the H8/38347 Group and H8/38447 Group.
Page 283 Section 8 I/O Ports 1. Port Data Register 9 (PDR9) Initial value Read/Write PDR9 is an 8-bit register that stores data for port 9 pins P9 to P9 . If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read.
Page 284: Pin Functions
Section 8 I/O Ports 8.10.3 Pin Functions Table 8.27 shows the port 9 pin functions. The SGX = 0 setting also functions on the H8/38347 and H8/38447. Table 8.27 Port 9 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR9 in PCR9 and bits SGX and SGS3 to SGS0 in LPCR.
Page 285: Pin States
Section 8 I/O Ports Pin Functions and Selection Method /SEG The pin function depends on bit PCR9 in PCR9 and bits SGS3 to SGS0 in /SEG LPCR. (n = 3 to 0) SGS3 to SGS0 0000 Not 0000 PCR9 Pin function input pin output pin output pin...
Page 286: Port A
Section 8 I/O Ports 8.11 Port A 8.11.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8.10. /COM /COM Port A /COM /COM Figure 8.10 Port A Pin Configuration 8.11.2 Register Configuration and Description Table 8.29 shows the port A register configuration. Table 8.29 Port A Registers Name Abbr.
Page 287 Section 8 I/O Ports 2. Port Control Register A (PCRA) — — — — PCRA PCRA PCRA PCRA Initial value Read/Write — — — — PCRA controls whether each of port A pins PA to PA functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 288: Pin Functions
Section 8 I/O Ports 8.11.3 Pin Functions Table 8.30 shows the port A pin functions. Table 8.30 Port A Pin Functions Pin Functions and Selection Method /COM The pin function depends on bit PCRA in PCRA and bits SGS3 to SGS0. SGS3 to SGS0 0000 Not 0000...
Page 289: Port B
Section 8 I/O Ports 8.12 Port B 8.12.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8.11. Port B Figure 8.11 Port B Pin Configuration 8.12.2 Register Configuration and Description Table 8.32 shows the port B register configuration. Table 8.32 Port B Register Name Abbr.
Page 290: Port C
Section 8 I/O Ports 8.13 Port C 8.13.1 Overview Port C is a 4-bit input-only port, configured as shown in figure 8.12. Port C Figure 8.12 Port C Pin Configuration 8.13.2 Register Configuration and Description Table 8.33 shows the port C register configuration. Table 8.33 Port C Register Name Abbr.
Page 291: Input/Output Data Inversion Function
Section 8 I/O Ports Reading the pin for which an analog input channel is selected by the AMR CH3 to CH0 of the A/D converter, "0" is read regardless of the input voltage. 8.14 Input/Output Data Inversion Function 8.14.1 Overview With input pins RXD , and RXD , and output pins TXD...
Page 292 Section 8 I/O Ports 1. Serial Port Control Register (SPCR) — — SPC32 SPC31 SCINV3 SCINV2 SCINV1 SCINV0 Initial value Read/Write — — SPCR is an 8-bit readable/writable register that performs RXD , RXD , TXD , and TXD input/output data inversion switching. SPCR is initialized to H'C0 by a reset. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved;...
Page 293 Section 8 I/O Ports Bit 3: TXD pin output data inversion switch Bit 3 specifies whether or not TXD pin output data is to be inverted. Bit 3 SCINV3 Description output data is not inverted (initial value) output data is inverted Bit 2: RXD pin input data inversion switch Bit 2 specifies whether or not RXD...
Page 294: Note On Modification Of Serial Port Control Register
Section 8 I/O Ports 8.14.3 Note on Modification of Serial Port Control Register When a serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying a serial port control register, do so in a state in which data changes are invalidated.
Page 295: Section 9 Timers
Section 9 Timers Section 9 Timers Overview This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event counter. The functions of these timers are outlined in table 9.1. Table 9.1 Timer Functions Event Waveform Name...
Page 296: Timer A
Section 9 Timers Event Waveform Name Functions Internal Clock Input Pin Output Pin Remarks • 16-bit counter Asynchro- — AEVL — nous event AEVH • Also usable as two counter independent 8-bit counters • Counts events asynchronous to φ and φ...
Page 297: Figure 9.1 Block Diagram Of Timer A
Section 9 Timers 2. Block Diagram Figure 9.1 shows a block diagram of timer A. CWORS φ φ /4 φ φ φ /128 φ φ TMOW φ/32 φ/8192, φ/4096, φ/2048, φ/16 φ/512, φ/256, φ/128, φ/8 φ/32, φ/8 φ/4 φ IRRTA Legend: TMA: Timer mode register A...
Page 298: Register Descriptions
Section 9 Timers 4. Register Configuration Table 9.3 shows the register configuration of timer A. Table 9.3 Timer A Registers Name Abbr. Initial Value Address Timer mode register A H'10 H'FFB0 Timer counter A H'00 H'FFB1 Clock stop register 1 CKSTPR1 H'FF H'FFFA...
Page 299 Section 9 Timers Bits 7 to 5: Clock output select (TMA7 to TMA5) Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz or 38.4 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode.
Page 300 Section 9 Timers Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 Bit 2 Bit 1 Bit 0 Prescaler and Divider Ratio TMA3 TMA2 TMA1...
Page 301 Section 9 Timers 2. Timer Counter A (TCA) TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA).
Page 302: Timer Operation
Section 9 Timers 4. Subclock Output Select Register (CWOSR) Bit: CWOS — — — — — — — Initial value: Read/Write: CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin. CWOSR is initialized to H'FE by a reset. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved;...
Page 303: Timer A Operation States
Section 9 Timers Note: * For details on interrupts, see section 3.3, Interrupts. 2. Real-time Clock Time Base Operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA.
Page 304: Timer C
Section 9 Timers Timer C 9.3.1 Overview Timer C is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer C are given below. •...
Page 305: Figure 9.2 Block Diagram Of Timer C
Section 9 Timers 2. Block Diagram Figure 9.2 shows a block diagram of timer C. φ TMIC φ IRRTC Legend: : Timer mode register C : Timer counter C : Timer load register C IRRTC : Timer C overflow interrupt request flag : Prescaler S Figure 9.2 Block Diagram of Timer C 3.
Page 306: Register Descriptions
Section 9 Timers 4. Register Configuration Table 9.6 shows the register configuration of timer C. Table 9.6 Timer C Registers Name Abbr. Initial Value Address Timer mode register C H'18 H'FFB4 Timer counter C H'00 H'FFB5 Timer load register C H'00 H'FFB5 Clock stop register 1...
Page 307 Section 9 Timers Bits 6 and 5: Counter up/down control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter. Bit 6 Bit 5 TMC6 TMC5 Description TCC is an up-counter...
Page 308 Section 9 Timers 2. Timer Counter C (TCC) TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC).
Page 309: Timer Operation
Section 9 Timers 4. Clock Stop Register 1 (CKSTPR1) Bit: S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value: Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer C is described here. For details of the other bits, see the sections on the relevant modules.
Page 310 Section 9 Timers During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: For details on interrupts, see section 3.3, Interrupts. 2. Auto-reload Timer Operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer.
Page 311: Timer C Operation States
Section 9 Timers 9.3.4 Timer C Operation States Table 9.7 summarizes the timer C operation states. Table 9.7 Timer C Operation States Sub- Sub- Module Operation Mode Reset Active Sleep Watch active sleep Standby Standby Interval Reset Functions Functions Halted Functions/ Functions/ Halted...
Page 312: Usage Note
Section 9 Timers 9.3.5 Usage Note Note the following regarding the operation of timer C. (1) Counting errors caused by external event input Timer counter errors may occur under the following conditions. Conditions • An external event (TMIC) is used in subsleep mode. Symptom •...
Page 313: Timer F
Section 9 Timers Timer F 9.4.1 Overview Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL).
Page 314: Figure 9.3 Block Diagram Of Timer F
Section 9 Timers 2. Block Diagram Figure 9.3 shows a block diagram of timer F. φ IRRTFL TCRF φ TCFL TMIF Toggle Comparator TMOFL circuit OCRFL TCFH Toggle Match TMOFH Comparator circuit OCRFH TCSRF IRRTFH Legend: TCRF: Timer control register F TCSRF: Timer control/status register F TCFH:...
Page 315: Table 9.8 Pin Configuration
Section 9 Timers 3. Pin Configuration Table 9.8 shows the timer F pin configuration. Table 9.8 Pin Configuration Name Abbr. Function Timer F event input TMIF Input Event input pin for input to TCFL Timer FH output TMOFH Output Timer FH toggle output pin Timer FL output TMOFL Output...
Page 316: Register Descriptions
Section 9 Timers 9.4.2 Register Descriptions 1. 16-bit Timer Counter (TCF) 8-bit Timer Counter (TCFH) 8-bit Timer Counter (TCFL) Bit: Initial value: Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL.
Page 317 Section 9 Timers 2. 16-bit Output Compare Register (OCRF) 8-bit Output Compare Register (OCRFH) 8-bit Output Compare Register (OCRFL) OCRF Bit: Initial value: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read/Write: OCRFH OCRFL OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL.
Page 318 Section 9 Timers 3. Timer Control Register F (TCRF) Bit: TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value: Read/Write: TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins.
Page 319 Section 9 Timers Bit 3: Toggle output level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL Description Low level (initial value) High level Bits 2 to 0: Clock select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input.
Page 320 Section 9 Timers 4. Timer Control/Status Register F (TCSRF) Bit: OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value: Read/Write: R/(W) * R/(W) * R/(W) * R/(W) * Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Page 321 Section 9 Timers Bit 5: Timer overflow interrupt enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH Description TCFH overflow interrupt request is disabled (initial value) TCFH overflow interrupt request is enabled Bit 4: Counter clear H (CCLRH) In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
Page 322 Section 9 Timers Bit 2: Compare match flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 CMFL Description Clearing condition:...
Page 323: Cpu Interface
Section 9 Timers Bit 2: Timer F module standby mode control (TFCKSTP) Bit 2 controls setting and clearing of module standby mode for timer F. TFCKSTP Description Timer F is set to module standby mode Timer F module standby mode is cleared (initial value) 9.4.3 CPU Interface...
Page 324: Figure 9.4 Write Access To Tcr (Cpu → Tcf)
Section 9 Timers 1. Write Access Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte.
Page 325: Figure 9.5 Read Access To Tcf (Tcf → Cpu)
Section 9 Timers 2. Read Access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU.
Page 326: Operation
Section 9 Timers 9.4.4 Operation Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers.
Page 327: Figure 9.6 Tmofh/Tmofl Output Timing
Section 9 Timers 2. TCF Increment Timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw). b.
Page 328: Table 9.10 Timer F Operation Modes
Section 9 Timers 4. TCF Clear Timing TCF can be cleared by a compare match with OCRF. 5. Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. 6. Compare Match Flag set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
Page 329: Application Notes
Section 9 Timers 9.4.5 Application Notes The following types of contention and operation can occur when timer F is used. 1. 16-bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated.
Page 330 Section 9 Timers b. TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid.
Page 331: Figure 9.7 Clear Interrupt Request Flag When Interrupt Factor Generation Signal
Section 9 Timers Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2. After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. 3.
Page 332: Timer G
Section 9 Timers 4. Timer Counter (TCF) Read/Write When φw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of ±1.
Page 333: Figure 9.8 Block Diagram Of Timer G
Section 9 Timers • Use of module standby mode enables this module to be placed in standby mode independently when not used. 2. Block Diagram Figure 9.8 shows a block diagram of timer G. φ Level detector φw/4 ICRGF Noise Edge TMIG canceler...
Page 334: Register Descriptions
Section 9 Timers 3. Pin Configuration Table 9.11 shows the timer G pin configuration. Table 9.11 Pin Configuration Name Abbr. Function Input capture input TMIG Input Input capture input pin 4. Register Configuration Table 9.12 shows the register configuration of timer G. Table 9.12 Timer G Registers Name Abbr.
Page 335 Section 9 Timers When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3, Interrupts. TCG cannot be read or written by the CPU.
Page 336 Section 9 Timers ICRGR is initialized to H'00 upon reset. 4. Timer Mode Register G (TMG) Bit: OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value: R/(W) * R/(W) * Read/Write: Note: * Bits 7 and 6 can only be written with 0, for flag clearing. TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
Page 337 Section 9 Timers Bit 6: Timer overflow flag L (OVFL) Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is low, or in interval operation. This flag is set by hardware and cleared by software. It cannot be set by software.
Page 338 Section 9 Timers Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0) Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges of the input capture input signal. Bit 3 Bit 2 CCLR1...
Page 339: Noise Canceler
Section 9 Timers Bit 3: Timer G module standby mode control (TGCKSTP) Bit 3 controls setting and clearing of module standby mode for timer G. TGCKSTP Description Timer G is set to module standby mode Timer G module standby mode is cleared (initial value) 9.5.3 Noise Canceler...
Page 340: Operation
Section 9 Timers Therefore, after making a setting for use of the noise cancellation function, a pulse with at least five times the width of the sampling clock is a dependable input capture signal. Even if noise cancellation is not used, an input capture input signal pulse width of at least 2φ or 2φ necessary to ensure that input capture operations are performed properly Note: * An input capture signal may be generated when the NCS bit is modified.
Page 341 Section 9 Timers In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF (ICRGF), and input capture register GR (ICRGR) are all initialized to H'00. Following a reset, TCG starts incrementing on the φ/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG.
Page 342: Figure 9.11 Input Capture Input Timing (Without Noise Cancellation Function)
Section 9 Timers 3. Input Capture Input Timing a. Without noise cancellation function For input capture input, dedicated input capture functions are provided for rising and falling edges. Figure 9.11 shows the timing for rising/falling edge input capture input. Input capture input signal Input capture signal F...
Page 343: Figure 9.13 Timing Of Input Capture By Input Capture Input
Section 9 Timers 4. Timing of Input Capture by Input Capture Input Figure 9.13 shows the timing of input capture by input capture input Input capture signal Input capture H'XX register Figure 9.13 Timing of Input Capture by Input Capture Input 5.
Page 344: Application Notes
Section 9 Timers 6. Timer G Operation Modes Timer G operation modes are shown in table 9.13. Table 9.13 Timer G Operation Modes Module Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Input capture Reset Functions* Functions* Functions/ Functions/ Functions/ Halted...
Page 345: Table 9.14 Internal Clock Switching And Tcg Operation
Section 9 Timers Table 9.14 Internal Clock Switching and TCG Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from low level to low level Clock before switching Clock after switching Count clock Write to CKS1 and CKS0 Goes from low level to high level Clock before switching...
Page 346 Section 9 Timers Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from high level to high level Clock before switching Clock before switching Count clock Write to CKS1 and CKS0 Note: * The switchover is seen as a falling edge, and TCG is incremented. 2.
Page 347: Table 9.15 Input Capture Input Signal Input Edges Due To Input Capture Input Pin Switching
Section 9 Timers Table 9.15 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching, and Conditions for Their Occurrence Input Capture Input Signal Input Edge Conditions Generation of rising edge When TMIG is modified from 0 to 1 while the TMIG pin is high When NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceler...
Page 348: Figure 9.15 Port Mode Register Manipulation And Interrupt Enable Flag Clearing Procedure
Section 9 Timers When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag clearing.
Page 349: Timer G Application Example
Section 9 Timers 9.5.6 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 should both be set to 1 in TMG. Figure 9.16 shows an example of the operation in this case.
Page 350: Watchdog Timer
Section 9 Timers Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1.
Page 351: Register Descriptions
Section 9 Timers 3. Register Configuration Table 9.17 shows the register configuration of the watchdog timer. Table 9.17 Watchdog Timer Registers Name Abbr. Initial Value Address Timer control/status register W TCSRW H'AA H'FFB2 Timer counter W H'00 H'FFB3 Clock stop register 2 CKSTP2 H'FF H'FFFB...
Page 352 Section 9 Timers Bit 6: Timer counter W write enable (TCWE) Bit 6 controls the writing of data to TCW. Bit 6 TCWE Description Data cannot be written to TCW (initial value) Data can be written to TCW Bit 5: Bit 4 write inhibit (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW.
Page 353 Section 9 Timers Bit 2: Watchdog timer on (WDON) Bit 2 enables watchdog timer operation. Bit 2 WDON Description Watchdog timer operation is disabled (initial value) Clearing condition: Reset, or when TCSRWE = 1 and 0 is written in both B2WI and WDON Watchdog timer operation is enabled Setting condition:...
Page 354 Section 9 Timers 2. Timer Counter W (TCW) TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input clock is φ/8192 or φw/32. The TCW value can always be written or read by the CPU. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW.
Page 355: Timer Operation
Section 9 Timers 4. Port Mode Register 3 (PMR3) — — — — AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value Read/Write — — — — PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3 pins.
Page 356: Figure 9.18 Typical Watchdog Timer Operations (Example)
Section 9 Timers Figure 9.18 shows an example of watchdog timer operations. Example: φ = 2 MHz and the desired overflow period is 30 ms. 2 × 10 × 30 × 10 –3 = 7.3 8192 The value set in TCW should therefore be 256 – 8 = 248 (H'F8). TCW overflow H'FF H'F8...
Page 357: Watchdog Timer Operation States
Section 9 Timers 9.6.4 Watchdog Timer Operation States Table 9.18 summarizes the watchdog timer operation states. Table 9.18 Watchdog Timer Operation States Operation Module Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Reset Functions Functions Halted Functions/ Halted Halted Halted Halted* TCSRW...
Page 358: Asynchronous Event Counter (Aec)
Section 9 Timers Asynchronous Event Counter (AEC) 9.7.1 Overview The asynchronous event counter is incremented by external event clock input. 1. Features Features of the asynchronous event counter are given below. • Can count asynchronous events • Can count external events input asynchronously without regard to the operation of base clocks φ...
Page 359: Figure 9.19 Block Diagram Of Asynchronous Event Counter
Section 9 Timers 2. Block Diagram Figure 9.19 shows a block diagram of the asynchronous event counter. IRREC ECCSR AEVH AEVL Legend: ECCSR : Event counter control/status register : Event counter H : Event counter L AEVH : Asynchronous event input H AEVL : Asynchronous event input L IRREC...
Page 360: Register Descriptions
Section 9 Timers 4. Register Configuration Table 9.20 shows the register configuration of the asynchronous event counter. Table 9.20 Asynchronous Event Counter Registers Name Abbr. Initial Value Address Event counter control/status register ECCSR H'00 H'FF95 Event counter H H'00 H'FF96 Event counter L H'00 H'FF97...
Page 361 Section 9 Timers Bit 7: Counter overflow flag H (OVH) Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by reading it when set to 1, then writing 0.
Page 362 Section 9 Timers Bit 4: Channel select (CH2) Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a 16-bit event counter which is incremented each time an event clock is input to the AEVL pin as asynchronous event input.
Page 363 Section 9 Timers Bit 2: Count-up enable L (CUEL) Bit 3 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled and increments the counter. When 0 is written to this bit, event clock input is disabled and the ECL value is held.
Page 364 Section 9 Timers 2. Event Counter H (ECH) ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial Value Read/Write ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. Either the external asynchronous event AEVH pin or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source by bit CH2.
Page 365: Operation
Section 9 Timers Bit 3: Asynchronous event counter module standby mode control (AECKSTP) Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter. AECKSTP Description Asynchronous event counter is set to module standby mode Asynchronous event counter module standby mode is cleared (initial value) 9.7.3 Operation...
Page 366: Figure 9.21 Example Of Software Processing When Using Ech And Ecl As 8-Bit Event Counters
Section 9 Timers occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. 2. 8-bit Event Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. Figure 9.21 shows an example of the software processing when ECH and ECL are used as 8-bit event counters.
Page 367: Asynchronous Event Counter Operation Modes
Section 9 Timers 9.7.4 Asynchronous Event Counter Operation Modes Asynchronous event counter operation modes are shown in table 9.21. Table 9.21 Asynchronous Event Counter Operation Modes Operation Module Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby ECCSR Reset Functions Functions Held* Functions...
Page 368 Section 9 Timers Maximum AEVH/AEVL Pin Mode Input Clock Frequency 16-bit mode H8/3847R Group • When not using the internal 8-bit mode Active (high-speed), sleep (high-speed) step-down circuit = 4.5 to 5.5 V/16 MHz = 2.7 to 5.5 V/10 MHz = 1.8 to 5.5 V/4 MHz •...
Page 369: Section 10 Serial Communication Interface
Section 10 Serial Communication Interface Section 10 Serial Communication Interface 10.1 Overview This LSI is provided with three serial communication interface (SCI) channels. The functions of the three SCI channels are summarized in table 10.1. Table 10.1 Overview of SCI Functions SCI Name Functions Features •...
Page 370: Sci1
Section 10 Serial Communication Interface 10.2 SCI1 10.2.1 Overview Serial communication interface 1 (SCI1) can carry out 8-bit or 16-bit serial data transfer in synchronous mode. It is also provided with a communication function called a Synchronized Serial Bus (SSB) that enables a number of ICs to be controlled. 1.
Page 371: Figure 10.1 Sci1 Block Diagram
Section 10 Serial Communication Interface 2. Block Diagram Figure 10.1 shows a block diagram of SCI1. φ φ SCR1 SCSR1 Transmit/receive control circuit Transfer bit counter SDRU SDRL IRRS1 Legend: SCR1: Serial control register 1 SCSR1: Serial control status register 1 SDRU: Serial data register U SDRL:...
Page 372: Register Descriptions
Section 10 Serial Communication Interface 3. Pin Configuration Table 10.2 shows the SCI1 pin configuration. Table 10.2 SCI1 Pin Configuration Name Abbr. Function SCI1 clock SCI1 clock input/output SCI1 data input Input SCI1 receive data input SCI1 data output Output SCI1 transmit data output 4.
Page 373 Section 10 Serial Communication Interface Bits 7 and 6: Operating mode select 1 and 0 (SNC1, SNC0) Bits 7 and 6 select the operating mode. Bit 7 Bit 6 SNC1 SNC0 Description 8-bit synchronous mode (initial value) 16-bit synchronous mode Continuous clock output mode * Reserved * Notes: 1.
Page 374 Section 10 Serial Communication Interface Bit 3: Clock source select 3 (CKS3) Bit 3 selects the clock source to be supplied and sets the SCK pin to input or output mode. Bit 3 CKS3 Description Clock source is prescaler S, SCK is output pin (initial value) Clock source is external clock, SCK...
Page 375 Section 10 Serial Communication Interface Bit 7: Reserved bit Bits 7 is reserved; it is always read as 1 and cannot be modified. Bit 6: Extension data bit (SOL) The SOL bit changes the output level of the SO pin. When read, SOL returns the output level of the SO pin.
Page 376 Section 10 Serial Communication Interface Bit 1: Tail mark transmission flag (MTRF) When MRKON = 1, bit 1 indicates that a tail mark is being transmitted. MTRF is a read-only bit, and cannot be modified. Bit 1 MTRF Description Idle state, or 8-bit/16-bit data transfer in progress (initial value) Tail mark transmission in progress Bit 0: Start flag (STF)
Page 377 Section 10 Serial Communication Interface SDRU read/write operations must only be performed after data transmission/reception has been completed. Data contents are not guaranteed if read/write operations are executed while data transmission/reception is in progress. The value of SDRU is undefined upon reset. 4.
Page 378: Operation
Section 10 Serial Communication Interface Bit 7: SCI1 module standby mode control (S1CKSTP) Bit 7 controls setting and clearing of module standby mode for SCI1. Bit 7 S1CKSTP Description SCI1 is set to module standby mode* SCI1 module standby mode is cleared (initial value) Note: * Setting to module standby mode resets SCR1, SCSR1, SDRU, and SDRL.
Page 379 Section 10 Serial Communication Interface 3. Data Transfer Operations Transmitting: The procedure for transmitting data is as follows. (1) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO and SCK pin functions. If necessary, also designate the SO pin as an NMOS open-drain output with bit POF1 in PMR2.
Page 380 Section 10 Serial Communication Interface (5) Read the transfer data from SDRL/SDRU. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL (6) If the serial clock continues to be input after the end of reception, this is regarded as an overrun state, and the ORER flag is set to 1 in SCSR1 (consequently, reception is not performed).
Page 381: Operation In Ssb Mode
Section 10 Serial Communication Interface 10.2.4 Operation in SSB Mode SSB communication uses two lines, SCL (Serial Clock) and SDA (Serial Data), and enables a number of ICs to be controlled when connected as shown in figure 10.3. In SSB mode, a tail mark is attached and transmitted following an 8-bit or 16-bit data transfer. Either HOLD TAIL or LATCH TAIL can be selected as the tail mark.
Page 382: Figure 10.4 Transfer Format (When Snc1 = 0, Snc0 = 1, Mrkon = 1)
Section 10 Serial Communication Interface Bit 14 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 15 Tail mark 1 frame Figure 10.4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1) 3. Tail Mark There are two tail marks: HOLD TAIL and LATCH TAIL.
Page 383 Section 10 Serial Communication Interface 4. Transmitting The procedure for transmitting data is as follows. (1) Set SOL to 1 in SCSR1. (2) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO and SCK pin functions. Set POF1 to 1 in PMR2 to designate the SO pin as an NMOS open-drain output.
Page 384: Interrupt Source
Section 10 Serial Communication Interface 10.2.5 Interrupt Source SCI1 has one interrupt source: transfer completion. When SCI1 completes transfer, IRRS1 is set to 1 in IRR1. The SCI1 interrupt source can be enabled or disabled by the IENS1 bit in IENR1. For details, see section 3.3, Interrupts.
Page 385: Sci3
Section 10 Serial Communication Interface 10.3 SCI3 10.3.1 Overview In addition to SCI1, this LSI has two serial communication interfaces, SCI3-1 and SCI3-2, with identical functions. In this manual, the generic term SCI3 is used to refer to both of these SCIs. Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode.
Page 386 Section 10 Serial Communication Interface  Synchronous mode Serial data communication is synchronized with a clock. In his mode, serial data can be exchanged with another LSI that has a synchronous communication function. Data length 8 bits Receive error detection Overrun errors •...
Page 387: Figure 10.6 Sci3 Block Diagram
Section 10 Serial Communication Interface 2. Block Diagram Figure 10.6 shows a block diagram of SCI3. Internal clock (φ/64, φ/16, φw/2, φ) External Baud rate generator clock Clock Transmit/receive SCR3 control circuit SPCR Interrupt request (TEI, TXI, RXI, ERI) Legend: RSR: Receive shift register RDR:...
Page 388: Table 10.4 Pin Configuration
Section 10 Serial Communication Interface 3. Pin Configuration Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration Name Abbr. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output 4.
Page 389: Register Descriptions
Section 10 Serial Communication Interface 10.3.2 Register Descriptions 1. Receive Shift Register (RSR)         Read/Write RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
Page 390 Section 10 Serial Communication Interface 3. Transmit Shift Register (TSR)         Read/Write TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD pin in order, starting from the LSB (bit 0).
Page 391 Section 10 Serial Communication Interface 5. Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value Read/Write SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time.
Page 392 Section 10 Serial Communication Interface Bit 5: Parity enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting.
Page 393 Section 10 Serial Communication Interface Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added.
Page 394 Section 10 Serial Communication Interface Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0) Bits 1 and 0 choose φ/64, φ/16, φ/2, or φ as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate register (BRR).
Page 395 Section 10 Serial Communication Interface Bit 7: Transmit interrupt enable (TIE) Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when transmit data is transferred from the transmit data register (TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to 1.
Page 396 Section 10 Serial Communication Interface Bit 5: Transmit enable (TE) Bit 5 selects enabling or disabling of the start of transmit operation. Bit 5 Description Transmit operation disabled * (TXD pin is I/O port) (initial value) Transmit operation enabled * (TXD pin is transmit data pin) Notes: 1.
Page 397 Section 10 Serial Communication Interface Bit 3: Multiprocessor interrupt enable (MPIE) Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1.
Page 398 Section 10 Serial Communication Interface After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR). For details on clock source selection, see table 10.12 in 10.3.3,1, Overview. Bit 1 Bit 0 Description CKE1 CKE0 Communication Mode Clock Source Pin Function...
Page 399 Section 10 Serial Communication Interface Bit 7: Transmit data register empty (TDRE) Bit 7 indicates that transmit data has been transferred from TDR to TSR. Bit 7 TDRE Description Transmit data written in TDR has not been transferred to TSR Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction...
Page 400 Section 10 Serial Communication Interface Bit 5: Overrun error (OER) Bit 5 indicates that an overrun error has occurred during reception. Bit 5 Description Reception in progress or completed * (initial value) Clearing condition: After reading OER = 1, cleared by writing 0 to OER An overrun error has occurred during reception * Setting condition: When reception is completed with RDRF set to 1...
Page 401 Section 10 Serial Communication Interface Bit 3: Parity error (PER) Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. Bit 3 Description Reception in progress or completed * (initial value) Clearing condition: After reading PER = 1, cleared by writing 0 to PER A parity error has occurred during reception * Setting condition:...
Page 402 Section 10 Serial Communication Interface Bit 1: Multiprocessor bit receive (MPBR) Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. Bit 1 is a read-only bit and cannot be modified. Bit 1 MPBR Description Data in which the multiprocessor bit is 0 has been received*...
Page 403: Table 10.6 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (1)
Section 10 Serial Communication Interface Table 10.6 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) 32.8 kHz 38.4 kHz 2 MHz 2.4576 MHz 4 MHz...
Page 404: Table 10.6 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (2)
Section 10 Serial Communication Interface Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) 10 MHz 16 MHz Bit Rate Error Error (bit/s) –0.25 2 0.03 0.16 0.16 –0.35 2 0.16 0.16 –0.79 — — — 0.16 —...
Page 405: Table 10.8 Maximum Bit Rate For Each Frequency (Asynchronous Mode)
Section 10 Serial Communication Interface Notes: 1. φ /2 clock is selected in active (medium- and high-speed) or sleep (medium- and high-speed) mode. 2. φ clock is selected in subactive or subsleep mode. SCI3 can be used only when the φ /2 is selected as the CPU clock in subactive or subsleep mode.
Page 406: Table 10.9 Examples Of Brr Settings For Various Bit Rates (Synchronous Mode) (1)
Section 10 Serial Communication Interface Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) 38.4 kHz 2 MHz 4 MHz Bit Rate (bit/s) n Error Error Error — — — — — — — — — —...
Page 407: Table 10.9 Examples Of Brr Settings For Various Bit Rates (Synchronous Mode) (2)
Section 10 Serial Communication Interface Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) 10 MHz 16 MHz Bit Rate (bit/s) n Error Error — — — — — — — — — — — — —...
Page 408: Table 10.10 Relation Between N And Clock
Section 10 Serial Communication Interface Notes: The value set in BRR is given by the following equation: — 1 (8 × 2 × B) where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) OSC: Value of φ...
Page 409 Section 10 Serial Communication Interface 9. Clock Stop Register 1 (CKSTPR1) S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules.
Page 410 Section 10 Serial Communication Interface Bits 7 to 6: Reserved bits Bits 7 to 6 are reserved; they are always read as 1 and cannot be modified. Bit 5: P4 /TXD pin function switch (SPC32) This bit selects whether pin P4 /TXD is used as P4 or as TXD...
Page 411 Section 10 Serial Communication Interface Bit 2: RXD pin input data inversion switch Bit 2 specifies whether or not RXD pin input data is to be inverted. Bit 2 SCINV2 Description input data is not inverted (initial value) input data is inverted Bit 1: TXD pin output data inversion switch Bit 1 specifies whether or not TXD...
Page 412: Operation
Section 10 Serial Communication Interface 10.3.3 Operation 1. Overview SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.11.
Page 413: Table 10.11 Smr Settings And Corresponding Data Transfer Formats
Section 10 Serial Communication Interface Table 10.11 SMR Settings and Corresponding Data Transfer Formats Data Transfer Format bit 7 bit 6 bit 2 bit 5 bit 3 Data Multiprocessor Parity Stop Bit STOP Mode Length Length Asynchronous 8-bit data No 1 bit mode 2 bits...
Page 414: Table 10.12 Smr And Scr3 Settings And Clock Source Selection
Section 10 Serial Communication Interface Table 10.12 SMR and SCR3 Settings and Clock Source Selection SCR3 bit 7 bit 1 bit 0 Transmit/Receive Clock COM CKE1 CKE0 Mode Clock Source SCK Pin Function Asynchronous Internal I/O port (SCK pin not used) mode Outputs clock with same frequency as bit rate External...
Page 415: Table 10.13 Transmit/Receive Interrupts
Section 10 Serial Communication Interface c. Interrupts and continuous transmission/reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10.13. Table 10.13 Transmit/Receive Interrupts Interrupt Flags Interrupt Request Conditions Notes RDRF When serial reception is performed The RXI interrupt routine reads the...
Page 416: Figure 10.7 (A) Rdrf Setting And Rxi Interrupt
Section 10 Serial Communication Interface RSR (reception in progress) RSR↑ (reception completed, transfer) RDRF ← 1 RDRF = 0 (RXI request when RIE = 1) Figure 10.7 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TSR (transmission in progress) TSR↓...
Page 417: Figure 10.8 Data Format In Asynchronous Communication
Section 10 Serial Communication Interface 2. Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Page 418: Table 10.14 Data Transfer Formats (Asynchronous Mode)
Section 10 Serial Communication Interface Table 10.14 Data Transfer Formats (Asynchronous Mode) Serial Data Transfer Format and Frame Length STOP 10 11 12 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 5-bit data...
Page 419: Figure 10.9 Phase Relationship Between Output Clock And Transfer Data (Asynchronous Mode) (8-Bit Data, Parity, 2 Stop Bits)
Section 10 Serial Communication Interface b. Clock Either an internal clock generated by the baud rate generator or an external clock input at the pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3.
Page 420: Figure 10.10 Example Of Sci3 Initialization Flowchart
Section 10 Serial Communication Interface Figure 10.10 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 Set clock selection in SCR3. Be sure to Set bits CKE1 clear the other bits to 0. If clock output and CKE0 is selected in asynchronous mode, the clock is output immediately after setting...
Page 421: Figure 10.11 Example Of Data Transmission Flowchart (Asynchronous Mode)
Section 10 Serial Communication Interface • Transmitting Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1,...
Page 422: Figure 10.12 Example Of Operation When Transmitting In Asynchronous Mode (8-Bit Data, Parity, 1 Stop Bit)
Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 423: Figure 10.13 Example Of Data Reception Flowchart (Asynchronous Mode)
Section 10 Serial Communication Interface • Receiving Figure 10.13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bits OER, Read bits OER, PER, and FER in the PER, FER in SSR serial status register (SSR) to determine if there is an error.
Page 424 Section 10 Serial Communication Interface If a receive error has Start receive occurred, read bits OER, error processing Overrun error PER, and FER in SSR to processing identify the error, and after carrying out the necessary error processing, ensure OER = 1? that bits OER, PER, and FER are all cleared to 0.
Page 425: Table 10.15 Receive Error Detection Conditions And Receive Data Processing
Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10.14.
Page 426: Figure 10.14 Example Of Operation When Receiving In Asynchronous Mode (8-Bit Data, Parity, 1 Stop Bit)
Section 10 Serial Communication Interface Figure 10.14 shows an example of the operation when receiving in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark state data data (idle state) Serial data 1 frame 1 frame RDRF RXI request RDRF 0 start bit ERI request in...
Page 427: Figure 10.15 Data Format In Synchronous Communication
Section 10 Serial Communication Interface a. Data transfer format The general data transfer format in synchronous communication is shown in figure 10.15. Serial clock Serial Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 data Don't Don't...
Page 428 Section 10 Serial Communication Interface c. Data transfer operations • SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in “SCI initialization” under 10.3.3, 2. c. Data transfer operations, and shown in figure 10.10. •...
Page 429: Figure 10.16 Example Of Data Transmission Flowchart (Synchronous Mode)
Section 10 Serial Communication Interface Start Sets bits SPC31 and SPC32 to 1 in SPCR Read the serial status register (SSR) and Read bit TDRE check that bit TDRE is set to 1, then write in SSR transmit data to the transmit data register (TDR).
Page 430: Figure 10.17 Example Of Operation When Transmitting In Synchronous Mode
Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 431: Figure 10.18 Example Of Data Reception Flowchart (Synchronous Mode)
Section 10 Serial Communication Interface • Receiving Figure 10.18 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bit OER Read bit OER in the serial status register in SSR (SSR) to determine if there is an error.
Page 432: Figure 10.19 Example Of Operation When Receiving In Synchronous Mode
Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Page 433: Figure 10.20 Example Of Simultaneous Data Transmission/Reception Flowchart (Synchronous Mode)
Section 10 Serial Communication Interface • Simultaneous transmit/receive Figure 10.20 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR Read the serial status register (SSR) and Read bit TDRE check that bit TDRE is set to 1, then write...
Page 434 Section 10 Serial Communication Interface 4. Multiprocessor Communication Function The multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. Serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data).
Page 435: Figure 10.21 Example Of Inter-Processor Communication Using Multiprocessor Format (Sending Data H'aa To Receiver A)
Section 10 Serial Communication Interface Sender Communication line Receiver A Receiver B Receiver C Receiver D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle Data transmission cycle (specifying the receiver) (sending data to the receiver...
Page 436: Figure 10.22 Example Of Multiprocessor Data Transmission Flowchart
Section 10 Serial Communication Interface Start Sets bits SPC31 and SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR).
Page 437: Figure 10.23 Example Of Operation When Transmitting Using Multiprocessor Format (8-Bit Data, Multiprocessor Bit, 1 Stop Bit)
Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 438: Figure 10.24 Example Of Multiprocessor Data Reception Flowchart
Section 10 Serial Communication Interface Start Set bit MPIE to 1 in SCR3. Set bit MPIE to 1 in SCR3 Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has Read bits OER occurred, execute receive error processing.
Page 439 Section 10 Serial Communication Interface Start receive error processing Overrun error processing OER = 1? Break? FER = 1? Framing error processing Clear bits OER and FER to 0 in SSR End of receive error processing Figure 10.24 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10.25 shows an example of the operation when receiving using the multiprocessor format.
Page 440: Figure 10.25 Example Of Operation When Receiving Using Multiprocessor Format (8-Bit Data, Multiprocessor Bit, 1 Stop Bit)
Section 10 Serial Communication Interface Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI request RDRF cleared No RXI request operation MPIE cleared to 0 RDR retains to 0 previous state...
Page 441: Interrupts
Section 10 Serial Communication Interface 10.3.4 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10.16.
Page 442: Application Notes
Section 10 Serial Communication Interface For further details, see section 3.3, Interrupts. 10.3.5 Application Notes The following points should be noted when using SCI3. 1. Relation between Writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR.
Page 443 Section 10 Serial Communication Interface 3. Break Detection and Processing When a framing error is detected, a break can be detected by reading the value of the RXD directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set.
Page 444: Figure 10.26 Receive Data Sampling Timing In Asynchronous Mode
Section 10 Serial Communication Interface 16 clock pulses 8 clock pulses 15 0 15 0 Internal basic clock Receive data Start bit (RXD3x) Synchronization sampling timing Data sampling timing Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1).
Page 445: Figure 10.27 Relation Between Rdr Read Timing And Data
Section 10 Serial Communication Interface 7. Relation between RDR Reads and Bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred.
Page 446 Section 10 Serial Communication Interface 9. Cautions on Switching of SCK Pin Function If the function of the SCK pin is switched from clock output to I/O port after using the SCI3 in clock synchronization mode, the “low” level is output in a moment (1/2 of the system clock φ) at the SCK pin function switching.
Page 447: Section 11 14-Bit Pwm
Section 11 14-Bit PWM Section 11 14-Bit PWM 11.1 Overview This LSI is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a D/A converter by connecting a low-pass filter. 11.1.1 Features Features of the 14-bit PWM are as follows. •...
Page 448: Block Diagram
Section 11 14-Bit PWM 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the 14-bit PWM. PWDRL PWDRU φ/2 φ/4 waveform φ/8 generator φ/16 PWCR Legend: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register Figure 11.1 Block Diagram of the 14 bit PWM 11.1.3 Pin Configuration...
Page 449: Register Configuration
Section 11 14-Bit PWM 11.1.4 Register Configuration Table 11.2 shows the register configuration of the 14-bit PWM. Table 11.2 Register Configuration Name Abbr. Initial Value Address PWM control register PWCR H'FC H'FFD0 PWM data register U PWDRU H'C0 H'FFD1 PWM data register L PWDRL H'00 H'FFD2...
Page 450 Section 11 14-Bit PWM Bits 1 and 0: Clock select 1 and 0 (PWCR1, PWCR0) Bits 1 and 0 select the clock supplied to the 14-bit PWM. These bits are write-only bits; they are always read as 1. Bit 1 Bit 0 PWCR1 PWCR0...
Page 451: Pwm Data Registers U And L (Pwdru, Pwdrl)
Section 11 14-Bit PWM 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU   PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 Initial value   Read/Write PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value Read/Write PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL.
Page 452: Clock Stop Register 2 (Ckstpr2)
Section 11 14-Bit PWM 11.2.3 Clock Stop Register 2 (CKSTPR2) — — — — AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value Read/Write — — — — CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the PWM is described here. For details of the other bits, see the sections on the relevant modules.
Page 453: Operation
Section 11 14-Bit PWM 11.3 Operation 11.3.1 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 3 (PMR3) to 1 so that pin P3 /PWM is designated for PWM output.
Page 454: Pwm Operation Modes
Section 11 14-Bit PWM 1 conversion period T = t ..t ..= t Figure 11.2 PWM Output Waveform 11.3.2 PWM Operation Modes PWM operation modes are shown in table 11.3. Table 11.3 PWM Operation Modes Operation Module Mode Reset Active Sleep...
Page 455: Section 12 A/D Converter
Section 12 A/D Converter Section 12 A/D Converter 12.1 Overview This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 12 channels of analog input. 12.1.1 Features The A/D converter has the following features. • 10-bit resolution •...
Page 456: Block Diagram
Section 12 A/D Converter 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG Multiplexer ADSR Com- Control logic parator – Reference voltage ADRRH ADRRL IRRAD Legend: AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion end interrupt request flag...
Page 457: Pin Configuration
Section 12 A/D Converter 12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbr. Function Analog power supply Input Power supply and reference voltage of analog part Analog ground Input Ground and reference voltage of analog part Analog input 0 Input Analog input channel 0...
Page 458: Register Descriptions
Section 12 A/D Converter 12.2 Register Descriptions 12.2.1 A/D Result Registers (ADRRH, ADRRL) ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 — — — — — — Initial value — — — — — — fixed fixed fixed fixed fixed fixed...
Page 459 Section 12 A/D Converter Bit 7: Clock select (CKS) Bit 7 sets the A/D conversion speed. Conversion Time (Active (High-Speed) Mode) * Bit 7 φ φ φ φ = 1 MHz φ φ φ φ = 5 MHz Conversion Period 62/φ...
Page 460: A/D Start Register (Adsr)
Section 12 A/D Converter Bits 3 to 0: Channel select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected...
Page 461: Clock Stop Register 1 (Ckstpr1)
Section 12 A/D Converter Bit 7: A/D start flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF Description Read: Indicates the completion of A/D conversion (initial value) Write: Stops A/D conversion Read: Indicates A/D conversion in progress Write: Starts A/D conversion Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved;...
Page 462: Operation
Section 12 A/D Converter 12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 10- bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
Page 463: A/D Converter Operation Modes
Section 12 A/D Converter 12.3.3 A/D Converter Operation Modes A/D converter operation modes are shown in table 12.3. Table 12.3 A/D Converter Operation Modes Operation Module Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Reset Functions Functions Held Held Held Held Held...
Page 464: Figure 12.3 Typical A/D Converter Operation Timing
Section 12 A/D Converter 6. The A/D interrupt handling routine ends. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 to 6 take place. Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter. Interrupt (IRRAD) Set *...
Page 465: Figure 12.4 Flow Chart Of Procedure For Using A/D Converter (Polling By Software)
Section 12 A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRRH/ADRRL data Perform A/D conversion? Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software) Rev.
Page 466: Application Notes
Section 12 A/D Converter Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Perform A/D conversion? Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used) 12.6 Application Notes 12.6.1...
Page 467: Permissible Signal Source Impedance
Section 12 A/D Converter • In active mode or sleep mode, analog power supply current (AI ) flows into the ladder STOP1 resistance even when the A/D converter is not operating. Therefore, if the A/D converter is not used, it is recommended that AV be connected to the system power supply and the ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop register 1 (CKSTPR1).
Page 468 Section 12 A/D Converter Rev. 6.00 Aug 04, 2006 page 430 of 680 REJ09B0145-0600...
Page 469: Section 13 Lcd Controller/Driver
Section 13 LCD Controller/Driver Section 13 LCD Controller/Driver 13.1 Overview This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 13.1.1 Features Features of the LCD controller/driver are given below. •...
Page 470: Block Diagram
Section 13 LCD Controller/Driver 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the LCD controller/driver. LCD drive power supply φ/2 to φ/256 Common Common φ data latch driver LPCR /DO* LCR2 40-bit shift Segment Display timing generator driver register LCD RAM (32 bytes)
Page 471: Pin Configuration
Section 13 LCD Controller/Driver 13.1.3 Pin Configuration Table 13.1 shows the LCD controller/driver pin configuration. Table 13.1 Pin Configuration Name Abbr. Function Segment output pins to SEG Output LCD segment drive pins All pins are multiplexed as port pins (setting programmable) Common output pins to COM Output...
Page 472: Register Descriptions
Section 13 LCD Controller/Driver 13.2 Register Descriptions 13.2.1 LCD Port Control Register (LPCR) DTS1 DTS0 SGS3 SGS2 SGS1 SGS0 Initial value Read/Write LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions. LPCR is initialized to H'00 upon reset. Bits 7 to 5: Duty cycle select 1 and 0 (DTS1, DTS0), common function select (CMX) The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty.
Page 473 Section 13 LCD Controller/Driver Bit 4: Expansion Signal Selection (SGX) Bit 4 (SGX) selects whether the SEG , SEG , SEG /DO, and SEG /M pins are used as segment pins (SEG to SEG ) or as segment external expansion signal pins (CL , CL , DO, and M).
Page 474: Lcd Control Register (Lcr)
Section 13 LCD Controller/Driver 13.2.2 LCD Control Register (LCR) — DISP CKS3 CKS2 CKS1 CKS0 Initial value Read/Write — LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and display data control, and selects the frame frequency. LCR is initialized to H'80 upon reset.
Page 475 Section 13 LCD Controller/Driver Bit 4: Display data control (DISP) Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. Bit 4 DISP Description Blank data is displayed (initial value) LCD RAM data is display Bits 3 to 0: Frame frequency select 3 to 0 (CKS3 to CKS0) Bits 3 to 0 select the operating clock and the frame frequency.
Page 476: Lcd Control Register 2 (Lcr2)
Section 13 LCD Controller/Driver 13.2.3 LCD Control Register 2 (LCR2) DTS1 DTS0 SGS3 SGS2 SGS1 SGS0 Initial value Read/Write LCR2 is an 8-bit read/write register which controls switching between the A waveform and B waveform, and selects the duty cycle of the charge/discharge pulses which control disconnection of the power supply split-resistance from the power supply circuit.
Page 477: Figure 13.2 Example Of A Waveform With 1/2 Duty And 1/2 Bias
Section 13 LCD Controller/Driver Bits 3 to 0: Charge/discharge pulse duty cycle select (CDS3 to CDS0) Bit 3 Bit 2 Bit 1 Bit 0 CDS3 CDS2 CDS1 CDS0 Duty Cycle Notes Fixed high (initial value) Fixed low 1/16 1/32 *: Don’t care Bits 3 to 0 select the duty cycle while the power supply split-resistance is connected to the power supply circuit.
Page 478: Clock Stop Register 2 (Ckstpr2)
Section 13 LCD Controller/Driver 13.2.4 Clock Stop Register 2 (CKSTPR2) — — — — AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value Read/Write — — — — CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the LCD controller/driver is described here. For details of the other bits, see the sections on the relevant modules.
Page 479: Operation
Section 13 LCD Controller/Driver 13.3 Operation 13.3.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. 1. Hardware Settings a. Using 1/2 duty When 1/2 duty is used, interconnect pins V and V as shown in figure 13.3.
Page 480: Figure 13.4 Examples Of Lcd Power Supply Pin Connections
Section 13 LCD Controller/Driver d. LCD drive power supply setting With this LSI, there are two ways of providing LCD power: by using the on-chip power supply circuit, or by using an external circuit. When the on-chip power supply circuit is used for the LCD drive power supply, the V pins should be interconnected externally, as shown in figure 13.4 (a).
Page 481 Section 13 LCD Controller/Driver 2. Software Settings a. Duty selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0. b. Segment selection The segment drivers to be used can be selected with bits SGS to SGS c.
Page 482: Relationship Between Lcd Ram And Display
Section 13 LCD Controller/Driver 13.3.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles with the segment not externally expanded are shown in figures 13.5 to 13.8, and ones with the segments externally expanded are shown in figures 13.9 to 13.12.
Page 483: Figure 13.6 Lcd Ram Map With Segments Not Externally Expanded (1/3 Duty)
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 H'F753 Space not used for display Figure 13.6 LCD RAM Map with Segments Not Externally Expanded (1/3 Duty) Rev. 6.00 Aug 04, 2006 page 445 of 680 REJ09B0145-0600...
Page 484: Figure 13.7 Lcd Ram Map With Segments Not Externally Expanded (1/2 Duty)
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Display space H'F74A Space not used for display H'F753 Figure 13.7 LCD RAM Map with Segments Not Externally Expanded (1/2 Duty) Rev.
Page 485: Figure 13.8 Lcd Ram Map With Segments Not Externally Expanded (Static Mode)
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Display space H'F745 Space not used for display H'F753 Figure 13.8 LCD RAM Map with Segments Not Externally Expanded (Static Mode) Rev.
Page 486: Figure 13.9 Lcd Ram Map With Segment Externally Expanded (Sgx = "1", Sgs3 To Sgs0 = "0000" 1/4 Duty)
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Expansion driver display space H'F75F Figure 13.9 LCD RAM Map with Segment Externally Expanded (SGX = “1”, SGS3 to SGS0 = “0000” 1/4 duty) Rev.
Page 487: Figure 13.10 Lcd Ram Map With Segment Externally Expanded (Sgx = "1", Sgs3 To Sgs0 = "0000" 1/3 Duty)
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Expansion driver display space H'F75F Space not used for display Figure 13.10 LCD RAM Map with Segment Externally Expanded (SGX = “1”, SGS3 to SGS0 = “0000”...
Page 488: Figure 13.11 Lcd Ram Map With Segment Externally Expanded (Sgx = "1", Sgs3 To Sgs0 = "0000" 1/2 Duty)
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Expansion driver display space H'F75F Figure 13.11 LCD RAM Map with Segment Externally Expanded (SGX = “1”, SGS3 to SGS0 = “0000” 1/2 duty) Rev.
Page 489: Figure 13.12 Lcd Ram Map With Segment Externally Expanded (Sgx = "1", Sgs3 To Sgs0 = "0000" Static)
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Expansion driver display space H'F75F Figure 13.12 LCD RAM Map with Segment Externally Expanded (SGX = “1”, SGS3 to SGS0 = “0000” static) Rev.
Page 490: Pin)
Section 13 LCD Controller/Driver 13.3.3 Luminance Adjustment Function (V Pin) Figure 13.13 shows a detailed block diagram of the LCD drive power supply unit. The voltage output to the V pin is V . When this voltage is used directly as the LCD drive power supply, the V and V pins should be shorted.
Page 491: Low-Power-Consumption Lcd Drive System
Section 13 LCD Controller/Driver 13.3.4 Low-Power-Consumption LCD Drive System The use of the built-in split-resistance is normally the easiest method for implementing the LCD power supply circuit, but since the built-in resistance is fixed, a certain direct current flows constantly from the built-in resistance’s V to V .
Page 492: Figure 13.14 Example Of Low-Power-Consumption Lcd Drive Operation
Section 13 LCD Controller/Driver 5. As can be seen from the above description, the capacitances and charging/discharging periods of the capacitors are determined by the current dissipation of the LCD panel used. The charging/discharging periods can be selected with bits CDS3 to CDS0. 6.
Page 493: Figure 13.15 Output Waveforms For Each Duty Cycle (A Waveform)
Section 13 LCD Controller/Driver 1 frame 1 frame Data Data (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame Data Data (d) Waveform with static output (c) Waveform with 1/2 duty Figure 13.15 Output Waveforms for Each Duty Cycle (A Waveform) Rev.
Page 494: Figure 13.16 Output Waveforms For Each Duty Cycle (B Waveform)
Section 13 LCD Controller/Driver 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame Data Data (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame...
Page 495: Operation In Power-Down Modes
Section 13 LCD Controller/Driver Table 13.3 Output Levels Data Static Common output Segment output 1/2 duty Common output Segment output 1/3 duty Common output Segment output 1/4 duty Common output Segment output 13.3.5 Operation in Power-Down Modes In this LSI, the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 13.4.
Page 496: Boosting The Lcd Drive Power Supply
Section 13 LCD Controller/Driver 13.3.6 Boosting the LCD Drive Power Supply When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case, the power supply impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 µF to pins V to V , as shown in figure 13.17, or by adding a split-resistance...
Page 497: Connection To Hd66100
Section 13 LCD Controller/Driver 13.3.7 Connection to HD66100 If the segments are to be expanded externally, an HD66100 should be connected. Connecting one HD66100 provides 80-segment expansion. When carrying out external expansion, select the external expansion signal function of pins SEG to SEG with the SGX bit in LPCR, and set bits SGS3 to SGS0 to 0000.
Page 498: Figure 13.18 Connection To Hd66100
Section 13 LCD Controller/Driver This LSI HD66100 (a) 1/3 bias, 1/4 duty or 1/3 duty This LSI HD66100 (b) 1/2 duty This LSI HD66100 (c) Static Figure 13.18 Connection to HD66100 Rev. 6.00 Aug 04, 2006 page 460 of 680 REJ09B0145-0600...
Page 499: Section 14 Power Supply Circuit
Section 14 Power Supply Circuit Section 14 Power Supply Circuit 14.1 Overview H8/3847R Group, H8/38347 Group and H8/38447 Group incorporate an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V to 3.2 V, independently of the voltage of the power supply connected to the external V pin.
Page 500: When Not Using Internal Power Supply Step-Down Circuit
Section 14 Power Supply Circuit 14.3 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the CV pin and V pin, as shown in figure 14.2. The external power supply is then input directly to the internal power supply.
Page 501: Section 15 Electrical Characteristics
Section 15 Electrical Characteristics Section 15 Electrical Characteristics 15.1 H8/3847R Group Absolute Maximum Ratings (Regular Specifications) Table 15.1 lists the absolute maximum ratings. Table 15.1 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Programming voltage –0.3 to +13.0...
Page 502: H8/3847R Electrical Characteristics (Regular Specifications)
Section 15 Electrical Characteristics 15.2 H8/3847R Electrical Characteristics (Regular Specifications) 15.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3847R Group are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range 16.0 38.4 32.768...
Page 503 Section 15 Electrical Characteristics 2. Power supply voltage and operating frequency range 19.2 16.384 (0.5) • Active (high-speed) mode 8.192 • Sleep (high-speed) mode (except CPU) • Internal power supply step-down circuit not used Note: Figures in parentheses are the minimum operating frequency of a case external clocks are used.
Page 504 Section 15 Electrical Characteristics 3. Analog power supply voltage and A/D converter operating range 1000 • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode • Internal power supply step-down circuit • Internal power supply step-down circuit not used not used and used •...
Page 505: Dc Characteristics
Section 15 Electrical Characteristics 15.2.2 DC Characteristics Table 15.2 lists the DC characteristics. Table 15.2 DC Characteristics = 0.0 V, Ta = –20°C to +75°C * = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV (including subactive mode) unless otherwise indicated.
Page 506 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes RES, WKP to WKP Input –0.3 — 0.2 V = 4.0 V to 5.5 V to IRQ , AEVL, voltage AEVH, TMIC, TMIF, TMIG, SCK , SCK –0.3 —...
Page 507 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes RES, P4 Input/ — — 20.0 µA = 0.5 V to output — — – 0.5 V leak- , P1 to P1 — — µA = 0.5 V to to P2 , P3 to P3...
Page 508 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Sub- — µA = 2.7 V, LCD on active 32 kHz crystal = φ mode oscillator (φ current — — µA = 2.7 V, LCD on dissi- 32 kHz crystal pation = φ...
Page 509 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Allow- –I All output pins — — = 4.0 V to 5.5 V able — — Except the above output high current (per pin) Allow- ∑ – I All output pins —...
Page 510: Ac Characteristics
Section 15 Electrical Characteristics 15.2.3 AC Characteristics Table 15.3 lists the control signal timing, and tables 15.4 and 15.5 list the serial interface timing. Table 15.3 Control Signal Timing = 0.0 V, Ta = –20°C to +75°C * = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV (including subactive mode) unless otherwise indicated.
Page 511 Section 15 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure External clock — — = 4.5 V to 5.5 V Figure 15.1 high width — — = 2.7 V to 5.5 V Figure 15.1 — — = 1.8 V to 5.5 V —...
Page 512 Section 15 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure to IRQ Input pin low — — Figure 15.3 width subcyc ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH UD pin minimum — — Figure 15.4 modulation width subcyc Notes: 1.
Page 513: Table 15.4 Serial Interface (Sci1) Timing
Section 15 Electrical Characteristics Table 15.4 Serial Interface (SCI1) Timing = 0.0 V, Ta = –20°C to +75°C * = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV unless otherwise indicated Values Applicable Reference Item Symbol Pins...
Page 514: Table 15.5 Serial Interface (Sci3-1, Sci3-2) Timing
Section 15 Electrical Characteristics Table 15.5 Serial Interface (SCI3-1, SCI3-2) Timing = 0.0 V, Ta = –20°C to +75°C * = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV (including subactive mode) unless otherwise indicated. Values Reference Item...
Page 515: A/D Converter Characteristics
Section 15 Electrical Characteristics 15.2.4 A/D Converter Characteristics Table 15.6 shows the A/D converter characteristics. Table 15.6 A/D Converter Characteristics = 0.0 V, Ta = –20°C to +75°C * = 1.8 V to 5.5 V, V = AV unless otherwise indicated. Values Applicable Item...
Page 516: Lcd Characteristics
Section 15 Electrical Characteristics 15.2.5 LCD Characteristics Table 15.7 shows the LCD characteristics. Table 15.7 LCD Characteristics = 0.0 V, Ta = –20°C to +75°C * = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV (including subactive mode) unless otherwise indicated.
Page 517: Table 15.8 Segment External Expansion Ac Characteristics
Section 15 Electrical Characteristics Table 15.8 Segment External Expansion AC Characteristics = 0.0 V, Ta = –20°C to +75°C * = 1.8 V to 5.5 V, V = AV (including subactive mode) unless otherwise indicated. Values Reference Applicable Test Item Symbol Pins Typ Max...
Page 518: H8/3847R Group Absolute Maximum Ratings (Wide-Range Specification)
Section 15 Electrical Characteristics 15.3 H8/3847R Group Absolute Maximum Ratings (Wide-range Specification) Table 15.9 lists the absolute maximum ratings. Table 15.9 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Programming voltage –0.3 to +13.0 Input voltage...
Page 519: H8/3847R Electrical Characteristics (Wide-Range Specification)
Section 15 Electrical Characteristics 15.4 H8/3847R Electrical Characteristics (Wide-range Specification) 15.4.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range 16.0 38.4 32.768...
Page 520 Section 15 Electrical Characteristics 2. Power supply voltage and operating frequency range 19.2 16.384 (0.5) • Active (high-speed) mode 8.192 • Sleep (high-speed) mode (except CPU) • Internal power supply step-down circuit not used Note: Figures in parentheses are the minimum operating frequency of a case external clocks are used.
Page 521 Section 15 Electrical Characteristics 3. Analog power supply voltage and A/D converter operating range 1000 • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode • Internal power supply step-down circuit • Internal power supply step-down circuit not used not used and used •...
Page 522: Dc Characteristics
Section 15 Electrical Characteristics 15.4.2 DC Characteristics Table 15.10 lists the DC characteristics. Table 15.10 DC Characteristics = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, Ta = –40°C to +85°C (including subactive mode) unless otherwise indicated.
Page 523 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes RES, WKP to WKP Input –0.3 — 0.2 V = 4.0 V to 5.5 V to IRQ , AEVL, voltage AEVH, TMIC, TMIF, TMIG, SCK , SCK –0.3 —...
Page 524 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes RES, P4 Input/ — — 20.0 µA = 0.5 V to output — — – 0.5 V leak- , P1 to P1 — — µA = 0.5 V to to P2 , P3 to P3...
Page 525 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Sub- — µA = 2.7 V, LCD on active 32 kHz crystal = φ mode oscillator (φ current — — µA = 2.7 V, LCD on dissi- 32 kHz crystal pation = φ...
Page 526 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Allow- –I All output pins — — = 4.0 V to 5.5 V able — — Except the above output high current (per pin) Allow- ∑ – I All output pins —...
Page 527: Ac Characteristics
Section 15 Electrical Characteristics 15.4.3 AC Characteristics Table 15.11 lists the control signal timing, and tables 15.12 and 15.13 list the serial interface timing. Table 15.11 Control Signal Timing = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, Ta = –40°C to +85°C (including subactive mode) unless otherwise indicated.
Page 528 Section 15 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure External clock — — = 4.5 V to 5.5 V Figure 15.1 high width — — = 2.7 V to 5.5 V Figure 15.1 — — = 1.8 V to 5.5 V —...
Page 529 Section 15 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure to IRQ Input pin low — — Figure 15.3 width subcyc ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH UD pin minimum — — Figure 15.4 modulation width subcyc Notes: 1.
Page 530: Table 15.12 Serial Interface (Sci1) Timing
Section 15 Electrical Characteristics Table 15.12 Serial Interface (SCI1) Timing = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, Ta = –40°C to +85°C unless otherwise indicated Values Applicable Reference Item Symbol Pins Unit Test Condition...
Page 531: Table 15.13 Serial Interface (Sci3-1, Sci3-2) Timing
Section 15 Electrical Characteristics Table 15.13 Serial Interface (SCI3-1, SCI3-2) Timing = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, Ta = –40°C to +85°C unless otherwise indicated. Values Reference Item Symbol Min Unit...
Page 532: A/D Converter Characteristics
Section 15 Electrical Characteristics 15.4.4 A/D Converter Characteristics Table 15.14 shows the A/D converter characteristics. Table 15.14 A/D Converter Characteristics = 1.8 V to 5.5 V, V = AV = 0.0 V, Ta = –40°C to +85°C unless otherwise indicated. Values Applicable Item...
Page 533: Lcd Characteristics
Section 15 Electrical Characteristics 15.4.5 LCD Characteristics Table 15.15 shows the LCD characteristics. Table 15.15 LCD Characteristics = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, Ta = –40°C to +85°C (including subactive mode) unless otherwise indicated.
Page 534: Table 15.16 Segment External Expansion Ac Characteristics
Section 15 Electrical Characteristics Table 15.16 Segment External Expansion AC Characteristics = 1.8 V to 5.5 V, V = AV = 0.0 V, Ta = –40°C to +85°C (including subactive mode) unless otherwise indicated. Applicable Values Reference Test Item Symbol Pins Typ Max Unit Conditions Figure...
Page 535: H8/3847S Group Absolute Maximum Ratings
Section 15 Electrical Characteristics 15.5 H8/3847S Group Absolute Maximum Ratings Table 15.17 lists the absolute maximum ratings. Table 15.17 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage –0.3 to +4.3 Analog power supply voltage –0.3 to +4.3 Input voltage Ports other than Port B, –0.3 to V...
Page 536: H8/3847S Group Electrical Characteristics
Section 15 Electrical Characteristics 15.6 H8/3847S Group Electrical Characteristics 15.6.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range 38.4 32.768 10.0...
Page 537 Section 15 Electrical Characteristics 2. Power supply voltage and operating frequency range 19.2 16.384 (0.5) • Active (high-speed) mode 8.192 • Sleep (high-speed) mode (except CPU) Note: Figures in parentheses are the minimum operating frequency of a case external clocks are used. When using an oscillator, the minimum operating frequency is φ=1MHz.
Page 538: Dc Characteristics
Section 15 Electrical Characteristics 15.6.2 DC Characteristics Table 15.18 lists the DC characteristics. Table 15.18 DC Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes RES, WKP to WKP Input 0.9 V — + 0.3 to IRQ high , AEVL, voltage AEVH, TMIC, TMIF, TMIG, SCK...
Page 539 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Output to P1 , P4 to P4 — — = 0.4 mA to P5 , P6 to P6 — — = 0.4 mA voltage to P7 , P8 to P8 to P9 , PA...
Page 540 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Active — Active (medium- OPE2 mode speed) mode current = 1.8 V, dissipa- = 2 MHz φ tion /128 — Active (medium- speed) mode = 3 V, = 4 MHz φ...
Page 541 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Watch — µA = 1.8 V, WATCH mode Ta = 25°C current 32 kHz crystal dissipa- oscillator tion LCD not used — = 2.7 V, Ta = 25°C 32 kHz crystal oscillator LCD not used...
Page 542 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Allowable ∑ – I All output pins — — 10.0 output high current (total) Notes: Connect the TEST pin to V 1. Pin States during Current Dissipation Measurement. Other Constant- RES Pin Internal State...
Page 543: Ac Characteristics
Section 15 Electrical Characteristics 15.6.3 AC Characteristics Table 15.19 lists the control signal timing, and tables 15.20 and 15.21 list the serial interface timing. Table 15.19 Control Signal Timing Values Applicable Reference Item Symbol Pins Unit Test Condition Figure System clock , OSC —...
Page 544 Section 15 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Oscillation , OSC — — Crystal Oscillator Figure 15.10 stabilization time Parameters Except the above — — Except the above X1, X2 — — = 2.2 V to 3.6 V —...
Page 545 Section 15 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure UD pin minimum — — Figure 15.4 modulation width subcyc Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 2. Figures in parentheses are the maximum t rate with external clock input.
Page 546: Table 15.20 Serial Interface (Sci1) Timing
Section 15 Electrical Characteristics Table 15.20 Serial Interface (SCI1) Timing Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Input clock cycle t — — Figure 15.5 Scyc Input clock high — — Figure 15.5 SCKH Scyc width Input clock low —...
Page 547: Table 15.21 Serial Interface (Sci3-1, Sci3-2) Timing
Section 15 Electrical Characteristics Table 15.21 Serial Interface (SCI3-1, SCI3-2) Timing Values Reference Item Symbol Min Unit Test Conditions Figure Input clock Asynchronous t — — Figure 15.6 Scyc cycle Synchronous — — subcyc Input clock pulse width — Figure 15.6 SCKW Scyc Transmit data delay time...
Page 548: A/D Converter Characteristics
Section 15 Electrical Characteristics 15.6.4 A/D Converter Characteristics Table 15.22 shows the A/D converter characteristics. Table 15.22 A/D Converter Characteristics Applicable Values Item Symbol Pins Unit Test Condition Notes Analog power — supply voltage Analog input to AN – 0.3 — voltage Analog power —...
Page 549: Lcd Characteristics
Section 15 Electrical Characteristics 15.6.5 LCD Characteristics Table 15.23 shows the LCD characteristics. Table 15.23 LCD Characteristics Applicable Values Test Item Symbol Pins Unit Conditions Notes Segment driver — — = 2 µA drop voltage = 2.7 V to 3.6 V Common driver —...
Page 550: Table 15.24 Segment External Expansion Ac Characteristics
Section 15 Electrical Characteristics Table 15.24 Segment External Expansion AC Characteristics Applicable Values Test Reference Item Symbol Pins Typ Max Unit Conditions Figure Clock high width , CL 800.0 — — Figure 15.8 Clock low width 800.0 — — Figure 15.8 Clock setup time , CL 500.0...
Page 551: Absolute Maximum Ratings Of H8/38347 Group And H8/38447 Group
Section 15 Electrical Characteristics 15.7 Absolute Maximum Ratings of H8/38347 Group and H8/38447 Group Table 15.25 lists the absolute maximum ratings. Table 15.25 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 –0.3 to +4.3 Analog power supply voltage –0.3 to +7.0 Input voltage...
Page 552: Electrical Characteristics Of H8/38347 Group And H8/38447 Group
Section 15 Electrical Characteristics 15.8 Electrical Characteristics of H8/38347 Group and H8/38447 Group 15.8.1 Power Supply Voltage and Operating Ranges The power supply voltage and operating ranges (shaded portions) are shown below. 1. Power Supply Voltage and Oscillation Frequency Range •...
Page 553 Section 15 Electrical Characteristics 2. Power Supply Voltage and Operating Frequency Range • H8/38347 Group 19.2 16.384 (0.5)* 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 1000 • Subactive mode • Subsleep mode (except CPU) • Watch mode (except CPU) 15.625 (7.813)* •...
Page 554 Section 15 Electrical Characteristics 3. Analog Power Supply Voltage and A/D Converter Operating Range • H8/38347 Group 1000 • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode • H8/38447 Group 1000 (0.5) • Active (high-speed) mode •...
Page 555: Dc Characteristics
Section 15 Electrical Characteristics 15.8.2 DC Characteristics Table 15.26 lists the DC characteristics. Table 15.26 DC Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Item Symbol Applicable Pins...
Page 556 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes RES, × 0.2 Input low – 0.3 — = 4.0 V to 5.5 V to WKP voltage , to IRQ AEVL, AEVH, TMIC, TMIF, × 0.1 – 0.3 —...
Page 557 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Output low to P1 — — = 4.0 V to 5.5 V voltage to P4 = 1.6 mA to P5 to P6 — — = 0.4 mA to P7 to P8 to P9...
Page 558 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Active — — Active (high-speed) OPE1 mode mode Approx. current = 2.7 V, max. value = 1.1 × consump- = 2 MHz tion Typ. — — Approx. max.
Page 559 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Active — — Active (medium- OPE2 mode speed) mode Approx. current = 2.7 V, max. value = 1.1 × consump- = 2 MHz, φ tion /128 Typ. —...
Page 560 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Sleep — — = 2.7 V, SLEEP mode = 2 MHz Approx. current max. value = 1.1 × consump- tion Typ. — — Approx. max. value = 1.1 × Typ.
Page 561 Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Subsleep — µA = 2.7 V, SUBSP mode LCD on, current 32-kHz crystal consump- resonator used = φ tion (φ Watch — — µA = 2.7 V, WATCH mode = 25°C,...
Page 562 Section 15 Electrical Characteristics Values Applicable Test Item Symbol Pins Unit Condition Notes Allowable output low Output pins — — = 4.0 V to current (per pin) except ports 2 5.5 V and 3 Ports 2 and 3 — — 10.0 = 4.0 V to 5.5 V...
Page 563 Section 15 Electrical Characteristics 3. Pin states when current consumption is measured LCD Power RES Pin Mode Internal State Other Pins Supply Oscillator Pins Active (high-speed) Only CPU operates Stops System clock: mode (I crystal resonator OPE1 Active (medium- Subclock: speed) mode (I Pin X = GND...
Page 564: Ac Characteristics
Section 15 Electrical Characteristics 15.8.3 AC Characteristics Table 15.27 lists the control signal timing and table 15.28 and 15.29 list the serial interface timing. Table 15.27 Control Signal Timing = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values...
Page 565 Section 15 Electrical Characteristics Values Applicable Reference Item Symbol Unit Test Condition Pins Figure External clock high — — Figure 15.1 * width — — = 4.5 to 5.5 V Figure 15.1 * — — = 2.7 to 5.5 V EXCL —...
Page 566: Table 15.28 Serial Interface (Sci1) Timing
Section 15 Electrical Characteristics Values Applicable Reference Item Symbol Unit Test Condition Pins Figure IRQ0 Input pin low — — Figure IRQ0 width 15.3 subcyc ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH UD pin minimum — — Figure transition width 15.4 subcyc Notes: 1.
Page 567: Table 15.29 Serial Interface (Sci3) Timing
Section 15 Electrical Characteristics Table 15.29 Serial Interface (SCI3) Timing = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Test Reference Item Symbol Typ Max Unit Condition Figure Input clock...
Page 568: A/D Converter Characteristics
Section 15 Electrical Characteristics 15.8.4 A/D Converter Characteristics Table 15.30 shows the A/D converter characteristics. Table 15.30 A/D Converter Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Applicable Test...
Page 569: Lcd Characteristics
Section 15 Electrical Characteristics 15.8.5 LCD Characteristics Table 15.31 shows the LCD characteristics. Table 15.31 LCD Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Applicable Reference Pins...
Page 570: Flash Memory Characteristics
Section 15 Electrical Characteristics 15.8.6 Flash Memory Characteristics Table 15.32 Flash Memory Characteristics Condition: = 2.7 V to 5.5 V, V = AV = 0.0 V, V = 2.7 V to 5.5 V (range of operating voltage when reading), V = 3.0 V to 5.5 V (range of operating voltage when programming/erasing), T = –20°C to +75°C (range of operating temperature...
Page 571 Section 15 Electrical Characteristics Values Test Item Symbol Unit Conditions Erase Wait time after — — µs SWE-bit setting * Wait time after — — µs ESU-bit setting * Wait time after — E-bit setting * α Wait time after —...
Page 572 Section 15 Electrical Characteristics 10. This is a data retain characteristic when reprogramming is performed within the specification range including this minimum value. Rev. 6.00 Aug 04, 2006 page 534 of 680 REJ09B0145-0600...
Page 573: Operation Timing
Section 15 Electrical Characteristics 15.9 Operation Timing Figures 15.1 to 15.8 show timing diagrams. , tw OSC1 EXCL Figure 15.1 Clock Input Timing Figure 15.2 RES RES Low Width to IRQ to WKP ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH Figure 15.3 Input Timing Rev.
Page 574: Figure 15.4 Ud Pin Minimum Modulation Width Timing
Section 15 Electrical Characteristics Figure 15.4 UD Pin Minimum Modulation Width Timing scyc or V or V SCKL SCKH SCKf SCKr Note: * Output timing reference levels Output high level = 1/2 V + 0.2 V Output low level = 0.8 V See figure 15.9 for the load conditions.
Page 575: Figure 15.6 Sck3 Input Clock Timing
Section 15 Electrical Characteristics SCKW scyc Figure 15.6 SCK3 Input Clock Timing scyc or V or V (transmit data) (receive data) Note: * Output timing reference levels Output high = 1/2 V + 0.2 V Output low = 0.8 V Load conditions are shown in figure 15.9.
Page 576: Figure 15.8 Segment Expansion Signal Timing
Section 15 Electrical Characteristics − 0.5 V 0.4 V − 0.5 V 0.4 V − 0.5 V 0.4 V 0.4 V Figure 15.8 Segment Expansion Signal Timing Rev. 6.00 Aug 04, 2006 page 538 of 680 REJ09B0145-0600...
Page 577: Output Load Circuit
Section 15 Electrical Characteristics 15.10 Output Load Circuit 2.4 kΩ Output pin 12 k Ω 30 pF Figure 15.9 Output Load Condition Rev. 6.00 Aug 04, 2006 page 539 of 680 REJ09B0145-0600...
Page 578: Resonator
Section 15 Electrical Characteristics 15.11 Resonator Ceramic Oscillator Parameters 4 MHz Manufacturer Products Name Frequency Manufacturer's Publicly Released Values MURATA CSTLS Max. 8.8 ½ 4M00G 53/56 Max. 36 pF Crystal Oscillator Parameters Frequency 4.193 MHz Manufacturer Products Name Manufacturer's Publicly Released Values Nihon Denpa NR-18 Max.
Page 579: Usage Note
Section 15 Electrical Characteristics 15.12 Usage Note Each of the products covered in this manual satisfy the electrical characteristics indicated. However, the actual electrical characteristics, operating margin and noise margin may differ from the indicated values due to differences in the manufacturing process, built-in ROM, layout pattern and other factors.
Page 580 Section 15 Electrical Characteristics Rev. 6.00 Aug 04, 2006 page 542 of 680 REJ09B0145-0600...
Page 581: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set Appendix A CPU Instruction Set Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
Page 582 Appendix A CPU Instruction Set Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C B #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 —...
Page 583 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C B Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — B Rd8+Rs8 → Rd8 ADD.B Rs, Rd — W Rd16+Rs16 → Rd16 ADD.W Rs, Rd —...
Page 584 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C SHAL.B Rd — — SHAR.B Rd — — SHLL.B Rd — — SHLR.B Rd — — 0 ROTXL.B Rd — — ROTXR.B Rd —...
Page 585 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C B (Rn8 of @Rd16) ← 0 BCLR Rn, @Rd — — — — — — 8 B (Rn8 of @aa:8) ← 0 BCLR Rn, @aa:8 —...
Page 586 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C B C∧(#xx:3 of Rd8) → C BIAND #xx:3, Rd — — — — — B C∧(#xx:3 of @Rd16) → C BIAND #xx:3, @Rd —...
Page 587 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C — PC ← Rn16 JMP @Rn — — — — — — 4 — PC ← aa:16 JMP @aa:16 — — — — — — 6 —...
Page 588 Appendix A CPU Instruction Set (3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) The number of states required for execution is 4n + 9 in the H8/3847R Group and 4n + 8 in the H8/3847S Group, H8/38347 Group and H8/38447 Group (n = value of R4L).
Page 589: Operation Code Map
Appendix A CPU Instruction Set Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 590 Appendix A CPU Instruction Set Rev. 6.00 Aug 04, 2006 page 552 of 680 REJ09B0145-0600...
Page 591: Number Of Execution States
Appendix A CPU Instruction Set Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I ×...
Page 592 Appendix A CPU Instruction Set Table A.3 Number of Cycles in Each Instruction Execution Status Access Location (instruction cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation 2 or 3 * Byte data access Word data access —...
Page 593 Appendix A CPU Instruction Set Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd...
Page 594 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd...
Page 595 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd...
Page 596 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic MOV.B Rs, @(d:16, MOV.B Rs, @–Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd MOV.W @(d:16, Rs), MOV.W @Rs+, Rd...
Page 597 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd POP Rd PUSH PUSH Rs SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd...
Page 598: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Appendix B Internal I/O Registers Addresses Upper Address: H'F0 Bit Names Lower Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'20 FLMCR1 —...
Page 599 Appendix B Internal I/O Registers Upper Address: H'FF Lower Register Bit Names Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'90 WEGR WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 System control H'91 SPCR...
Page 600 Appendix B Internal I/O Registers Lower Register Bit Names Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'B2 TCSRW B6WI TCWE B4WI TCSRWE B2WI WDON BOW1 WRST Watchdog timer H'B3 TCW7...
Page 601 Appendix B Internal I/O Registers Lower Register Bit Names Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'D9 PDR6 I/O Port H'DA PDR7 H'DB PDR8 H'DC PDR9 H'DD PDRA —...
Page 602: Functions
Appendix B Internal I/O Registers Functions Register Register Address to which the Name of acronym name register is mapped on-chip supporting module TMC—Timer mode register C H'B4 Timer C numbers Initial bit TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 values Initial value Names of the...
Page 603 Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 H'F020 Flash Memory  Initial value  Read/Write Program 0 Program mode cleared (initial value) 1 Transition to program mode [Setting condition] When SWE = 1 and PSU = 1 Erase 0 Erase mode cleared (initial value) 1 Transition to erase mode...
Page 604 Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 H'F021 Flash Memory        FLER Initial value        Read/Write Flash memory error Note: A write to FLMCR2 is prohibited. FLPWCR—Flash Memory Power Control Register H'F022 Flash Memory...
Page 605 Appendix B Internal I/O Registers EBR—Erase Block Register H'F023 Flash Memory Initial value Read/Write Blocks 7 to 0 0 When a block of EB7 to EB0 is not selected (initial value) 1 When a block of EB7 to EB0 is selected Note: Set the bit of EBR to H'00 when erasing.
Page 606 Appendix B Internal I/O Registers WEGR—Wakeup Edge Select Register H'90 System control WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WKPn edge selected WKPn pin falling edge detected WKPn pin rising edge detected (n = 0 to 7) Rev.
Page 607 Appendix B Internal I/O Registers SPCR—Serial Port Control Register H'91 — — SPC32 SPC31 SCINV3 SCINV2 SCINV1 SCINV0 Initial value Read/Write — — pin input data inversion switch input data is not inverted input data is inverted pin output data inversion switch output data is not inverted output data is inverted pin input data inversion switch...
Page 608 Appendix B Internal I/O Registers CWOSR—Subclock Output Select Register H'92 Timer A — — — — — — — CWOS Initial value Read/Write TMOW pin clock select Clock output from TMA is output φ is output Rev. 6.00 Aug 04, 2006 page 570 of 680 REJ09B0145-0600...
Page 609 Appendix B Internal I/O Registers ECCSR—Event Counter Control/Status Register H'95  CUEH CUEL CRCH CRCL Initial value R/(W) * R/(W) * Read/Write Counter reset control L ECL is reset ECL reset is cleared and count-up function is enabled Counter reset control H ECH is reset ECH reset is cleared and count-up function is enabled...
Page 610 Appendix B Internal I/O Registers ECH—Event Counter H H'96 ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial value Read/Write Count value Note: * ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit event counter (EC).
Page 611 Appendix B Internal I/O Registers SMR31—Serial Mode Register 31 H'98 SCI31 COM31 CHR31 PE31 PM31 STOP31 MP31 CKS311 CKS310 Initial value Read/Write Clock select φ clock φw/2 clock φ/16 clock φ/64 clock Multiprocessor mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop bit length 1 stop bit...
Page 612 Appendix B Internal I/O Registers BRR31—Bit Rate Register 31 H'99 SCI31 BRR317 BRR316 BRR315 BRR314 BRR313 BRR312 BRR311 BRR310 Initial value Read/Write Serial transmit/receive bit rate Rev. 6.00 Aug 04, 2006 page 574 of 680 REJ09B0145-0600...
Page 613 Appendix B Internal I/O Registers SCR31—Serial Control Register 31 H'9A SCI31 TIE31 RIE31 TE31 RE31 MPIE31 TEIE31 CKE311 CKE310 Initial value Read/Write Clock enable Description Bit 1 Bit 0 CKE311 CKE310 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock...
Page 614 Appendix B Internal I/O Registers TDR31—Transmit Data Register 31 H'9B SCI31 TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310 Initial value Read/Write Data for transfer to TSR Rev. 6.00 Aug 04, 2006 page 576 of 680 REJ09B0145-0600...
Page 615 Appendix B Internal I/O Registers SSR31—Serial Status Register31 H'9C SCI3 TDRE31 RDRF31 OER31 FER31 PER31 TEND31 MPBR31 MPBT31 Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received...
Page 616 Appendix B Internal I/O Registers RDR31—Receive Data Register 31 H'9D SCI31 RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310 Initial value Read/Write Serial receiving data are stored Rev. 6.00 Aug 04, 2006 page 578 of 680 REJ09B0145-0600...
Page 617 Appendix B Internal I/O Registers SCR1—Serial Control Register 1 H'A0 SCI1 SNC1 SNC0 MRKON LTCH CKS3 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 Serial Clock Cycle Prescaler Bit 2 Bit 1 Bit 0 Clock Cycle Division φ...
Page 618 Appendix B Internal I/O Registers SCSR1—Serial Control Status Register 1 H'A1 SCI1     ORER MTRF Initial value     Read/Write R/(W) Start flag Read Transfer operation stopped Write Invalid Read Transfer operation in progress Write Starts transfer operation Tail mark transmission flag 0 Idle state, or 8-bit/16-bit data transfer in progress...
Page 619 Appendix B Internal I/O Registers SDRU—Serial Data Register U H'A2 SCI1 SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Used for transmit data setting and receive data storage 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data register SDRL—Serial Data Register L...
Page 620 Appendix B Internal I/O Registers SMR32—Serial Mode Register 32 H'A8 SCI32 COM32 CHR32 PE32 PM32 STOP32 MP32 CKS321 CKS320 Initial value Read/Write Clock select φ clock φw/2 clock φ/16 clock φ/64 clock Multiprocessor mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop bit length 1 stop bit...
Page 621 Appendix B Internal I/O Registers BRR32—Bit Rate Register 32 H'A9 SCI32 BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR3120 Initial value Read/Write Serial transmit/receive bit rate Rev. 6.00 Aug 04, 2006 page 583 of 680 REJ09B0145-0600...
Page 622 Appendix B Internal I/O Registers SCR32—Serial Control Register 32 H'AA SCI32 TIE32 RIE32 TE32 RE32 MPIE32 TEIE32 CKE321 CKE320 Initial value Read/Write Clock enable Description Bit 1 Bit 0 CKE321 CKE320 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock...
Page 623 Appendix B Internal I/O Registers TDR32—Transmit Data Register 32 H'AB SCI32 TDR327 TDR326 TDR325 TDR324 TDR323 TDR322 TDR321 TDR320 Initial value Read/Write Data for transfer to TSR Rev. 6.00 Aug 04, 2006 page 585 of 680 REJ09B0145-0600...
Page 624 Appendix B Internal I/O Registers SSR32—Serial Status Register 32 H'AC SCI32 TDRE32 RDRF32 OER32 FER32 PER32 TEND32 MPBR32 MPBT32 Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received...
Page 625 Appendix B Internal I/O Registers RDR32—Receive Data Register 32 H'AD SCI32 RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320 Initial value Read/Write Serial receiving data are stored Rev. 6.00 Aug 04, 2006 page 587 of 680 REJ09B0145-0600...
Page 626 Appendix B Internal I/O Registers TMA—Timer Mode Register A H'B0 Timer A TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Initial value Read/Write — Clock output select* Internal clock select φ/32 Prescaler and Divider Ratio φ/16 TMA3 TMA2 TMA1 TMA0 or Overflow Period Function 0 0 1...
Page 627 Appendix B Internal I/O Registers TCA—Timer Counter A H'B1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write Count value Rev. 6.00 Aug 04, 2006 page 589 of 680 REJ09B0145-0600...
Page 628 Appendix B Internal I/O Registers TCSRW—Timer Control/Status Register W H'B2 Watchdog timer B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST Initial value Read/Write R/(W) R/(W) R/(W) R/(W) Watchdog timer reset 0 [Clearing conditions] • Reset by RES pin • When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 [Setting condition] When TCW overflows and a reset signal is generated Bit 0 write inhibit...
Page 629 Appendix B Internal I/O Registers TCW—Timer Counter W H'B3 Watchdog timer TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write Count value TMC—Timer Mode Register C H'B4 Timer C   TMC7 TMC6 TMC5 TMC2 TMC1 TMC0 Initial value ...
Page 630 Appendix B Internal I/O Registers TCC—Timer Counter C H'B5 Timer C TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write Count value Note: TCC is assigned to the same address as TLC. In a read, the TCC value is read. TLC—Timer Load Register C H'B5 Timer C...
Page 631 Appendix B Internal I/O Registers TCRF—Timer Control Register F H'B6 Timer F TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write Clock select L Counting on external event (TMIF) rising/falling edge Internal clock φ/32 Internal clock φ/16 Internal clock φ/4 Internal clock φw/4 Toggle output level L Low level...
Page 632 Appendix B Internal I/O Registers TCSRF—Timer Control/Status Register F H'B7 Timer F OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Counter clear L TCFL clearing by compare match is disabled TCFL clearing by compare match is enabled Timer overflow interrupt enable L TCFL overflow interrupt request is disabled...
Page 633 Appendix B Internal I/O Registers TCFH—8-Bit Timer Counter FH H'B8 Timer F TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 Initial value Read/Write Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF).
Page 634 Appendix B Internal I/O Registers OCRFL—Output Compare Register FL H'BB Timer F OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Initial value Read/Write Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF).
Page 635 Appendix B Internal I/O Registers TMG—Timer Mode Register G H'BC Timer G OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value Read/Write R/(W)* R/(W)* Clock select Internal clock: counting on φ /64 Internal clock: counting on φ /32 Internal clock: counting on φ /2 Internal clock: counting on φ...
Page 636 Appendix B Internal I/O Registers ICRGF—Input Capture Register GF H'BD Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write Stores TCG value at falling edge of input capture signal ICRGR—Input Capture Register GR H'BE Timer G ICRGR7 ICRGR6 ICRGR5...
Page 637 Appendix B Internal I/O Registers LPCR—LCD Port Control Register H'C0 LCD controller/driver DTS1 DTS0 SGS3 SGS2 SGS1 SGS0 Initial value Read/Write Segment driver select Function of Pins SEG to SEG Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes SGS3 SGS2...
Page 638 Appendix B Internal I/O Registers LCR—LCD Control Register H'C1 LCD controller/driver  DISP CKS3 CKS2 CKS1 CKS0 Initial value  Read/Write Frame frequency select Bit 1 Bit 1 Bit 3 Bit 2 Operating Clock CKS3 CKS2 CKS1 CKS0 φw φw/2 φw/4 φ/2 φ/4...
Page 639 Appendix B Internal I/O Registers LCR2—LCD Control Register 2 H'C2 LCDAB Ñ Ñ Ñ CDS3 CDS2 CDS1 CDS0 Initial value Read/Write Ñ Ñ Charge/discharge pulse duty cycle select Bit 1 Bit 0 Bit 3 Bit 2 Duty Cycle CDS3 CDS2 CDS1 CDS0 1/16...
Page 640 Appendix B Internal I/O Registers ADRRH—A/D Result Register H H'C4 A/D converter ADRRL—A/D Result Register L H'C5 ADRRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write A/D conversion result ADRRL ADR1 ADR0...
Page 641 Appendix B Internal I/O Registers AMR—A/D Mode Register H'C6 A/D converter   TRGE Initial value   Read/Write Channel select Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected * Don't care External trigger select 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG...
Page 642 Appendix B Internal I/O Registers ADSR—A/D Start Register H'C7 A/D converter ADSF — — — — — — — Initial value Read/Write — — — — — — — A/D status flag Indicates completion of A/D conversion Read Write Stops A/D conversion Read Indicates A/D conversion in progress Starts A/D conversion...
Page 643 Appendix B Internal I/O Registers PMR1—Port Mode Register 1 H'C8 I/O port IRQ3 IRQ2 IRQ1 IRQ4 TMIG TMOFH TMOFL TMOW Initial value Read/Write /TMOW pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOW output pin /TMOFL pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOFL output pin...
Page 644 Appendix B Internal I/O Registers PMR2—Port Mode Register 2 H'C9 I/O port • • • • H8/3847R Group and H8/3847S Group — — POF1 — — SCK1 Initial value Read/Write — — — — /SCK pin function switch 0 Functions as P2 I/O pin Functions as SCK I/O pin...
Page 645 Appendix B Internal I/O Registers • • • • H8/38347 Group and H8/38447 Group EXCL — POF1 — — SCK1 Initial value Read/Write — — — /SCK pin function switch 0 Functions as P2 I/O pin Functions as SCK I/O pin pin function switch 0 Functions as P2 I/O pin...
Page 646 Appendix B Internal I/O Registers PMR3—Port Mode Register 3 H'CA I/O port AEVL AEVH WDCKS IRQ0 RESO* Initial value Read/Write /PWM pin function switch 0 Functions as P3 I/O pin 1 Functions as PWM output pin /UD pin function switch 0 Functions as P3 I/O pin 1 Functions as UD input pin...
Page 647 Appendix B Internal I/O Registers PMR4—Port Mode Register 4 H'CB I/O port NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 Initial value Read/Write 0 P2 is CMOS output 1 P2 is NMOS open-drain output (n = 7 to 0) PMR5—Port Mode Register 5 H'CC I/O port Initial value...
Page 648 Appendix B Internal I/O Registers PWCR—PWM Control Register H'D0 14-bit PWM       PWCR1 PWCR0 Initial value       Read/Write Clock select 0 The input clock is φ/2 (tφ* = 2/φ) The conversion period is 16,384/φ, with a minimum modulation width of 1/φ The input clock is φ/4 (tφ* = 4/φ) The conversion period is 32,768/φ, with a minimum modulation width of 2/φ...
Page 649 Appendix B Internal I/O Registers PDR1—Port Data Register 1 H'D4 I/O ports Initial value Read/Write Data for port 1 pins PDR2—Port Data Register 2 H'D5 I/O ports Initial value Read/Write Data for port 2 pins PDR3—Port Data Register 3 H'D6 I/O ports Initial value Read/Write...
Page 650 Appendix B Internal I/O Registers PDR5—Port Data Register 5 H'D8 I/O ports Initial value Read/Write Data for port 5 pins PDR6—Port Data Register 6 H'D9 I/O ports Initial value Read/Write Data for port 6 pins PDR7—Port Data Register 7 H'DA I/O ports Initial value Read/Write...
Page 651 Appendix B Internal I/O Registers PDR9—Port Data Register 9 H'DC I/O ports Initial value Read/Write Data for port 9 pins PDRA—Port Data Register A H'DD I/O ports     Initial value     Read/Write Data for port A pins PDRB—Port Data Register B H'DE I/O ports...
Page 652 Appendix B Internal I/O Registers PUCR1—Port Pull-Up Control Register 1 H'E0 I/O ports PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 Initial value Read/Write Port 1 input pull-up MOS control Input pull-up MOS is off Input pull-up MOS is on Note: When the PCR1 specification is 0.
Page 653 Appendix B Internal I/O Registers PUCR5—Port Pull-Up Control Register 5 H'E2 I/O ports PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 Initial value Read/Write Port 5 input pull-up MOS control Input pull-up MOS is off Input pull-up MOS is on Note: When the PCR5 specification is 0.
Page 654 Appendix B Internal I/O Registers PCR1—Port Control Register 1 H'E4 I/O ports PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 Initial value Read/Write Port 1 input/output select 0 Input pin 1 Output pin PCR2—Port Control Register 2 H'E5 I/O ports PCR2 PCR2 PCR2...
Page 655 Appendix B Internal I/O Registers PCR4—Port Control Register 4 H'E7 I/O ports — — — — — PCR4 PCR4 PCR4 Initial value Read/Write — — — — — Port 4 input/output select 0 Input pin 1 Output pin PCR5—Port Control Register 5 H'E8 I/O ports PCR5...
Page 656 Appendix B Internal I/O Registers PCR7—Port Control Register 7 H'EA I/O ports PCR7 PCR7 PCR7 PCR7 PCR7 PCR7 PCR7 PCR7 Initial value Read/Write Port 7 input/output select 0 Input pin 1 Output pin PCR8—Port Control Register 8 H'EB I/O ports PCR8 PCR8 PCR8...
Page 657 Appendix B Internal I/O Registers PCRA—Port Control Register A H'ED I/O ports — — — — PCRA PCRA PCRA PCRA Initial value Read/Write — — — — Port A input/output select 0 Input pin 1 Output pin Rev. 6.00 Aug 04, 2006 page 619 of 680 REJ09B0145-0600...
Page 658 Appendix B Internal I/O Registers SYSCR1—System Control Register 1 H'F0 System control  SSBY STS2 STS1 STS0 LSON Initial value  Read/Write Active (medium-speed) mode clock select φ φ φ φ /128 Low speed on flag 0 The CPU operates on the system clock (φ) 1 The CPU operates on the subclock (φ...
Page 659 Appendix B Internal I/O Registers SYSCR2—System Control Register 2 H'F1 System control    NESEL DTON MSON Initial value    Read/Write Subactive mode clock select φ /8 φ /4 φ /2 Medium speed on flag *: Don't care 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct transfer on flag...
Page 660 Appendix B Internal I/O Registers IEGR—IRQ Edge Select Register H'F2 System control    IEG4 IEG3 IEG2 IEG1 IEG0 Initial value    Read/Write edge select 0 Falling edge of IRQ pin input is detected Rising edge of IRQ pin input is detected edge select 0 Falling edge of IRQ...
Page 661 Appendix B Internal I/O Registers IENR1—Interrupt Enable Register 1 H'F3 System control IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write to IRQ interrupt enable 0 Disables IRQ to IRQ interrupt requests Enables IRQ to IRQ interrupt requests Wakeup interrupt enable 0 Disables WKP to WKP...
Page 662 Appendix B Internal I/O Registers IENR2—Interrupt Enable Register 2 H'F4 System control IENDT IENAD — IENTG IENTFH IENTFL IENTC IENEC Initial value Read/Write Asynchronous event counter interrupt enable 0 Disables asynchronous event counter interrupt requests 1 Enables asynchronous event counter interrupt requests Timer C interrupt enable 0 Disables timer C interrupt requests...
Page 663 Appendix B Internal I/O Registers IRR1—Interrupt Request Register 1 H'F6 System control  IRRTA IRRS1 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value  R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write IRQ4 to IRQ0 interrupt request flags 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 1 [Setting condition]...
Page 664 Appendix B Internal I/O Registers IRR2—Interrupt Request Register 2 H'F7 System control IRRDT IRRAD — IRRTG IRRTFH IRRTFL IRRTC IRREC Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Asynchronous event counter interrupt request flag 0 [Clearing condition] When IRREC = 1, it is cleared by writing 0 1 [Setting condition] When the asynchronous event counter value overflows Timer C interrupt request flag...
Page 665 Appendix B Internal I/O Registers WPR—Wakeup Interrupt Request Register H'F9 System control IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Wakeup interrupt request register 0 [Clearing condition] When IWPFn = 1, it is cleared by writing 0 1 [Setting condition] When pin WKPn is designated for wakeup input and a falling edge is input at that pin...
Page 666 Appendix B Internal I/O Registers CKSTPR1—Clock Stop Register 1 H'FA System control S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write Timer A module standby mode control 0 Timer A is set to module standby mode Timer A module standby mode is cleared Timer C module standby mode control 0 Timer C is set to module standby mode Timer C module standby mode is cleared...
Page 667 Appendix B Internal I/O Registers CKSTPR2—Clock Stop Register 2 H'FB System control — — — — AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value Read/Write — — — — LCD module standby mode control 0 LCD is set to module standby mode LCD module standby mode is cleared PWM module standby mode control 0 PWM is set to module standby mode...
Page 668: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams Block Diagrams of Port 1 (low level during reset and in standby mode) PUCR1 PMR1 PDR1 PCR1 n − 4/n PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1:...
Page 669: Figure C.1 (B) Port 1 Block Diagram (Pin P1
Appendix C I/O Port Block Diagrams PUCR1 PMR1 PDR1 PCR1 Timer G module TMIG Figure C.1 (b) Port 1 Block Diagram (Pin P1 Rev. 6.00 Aug 04, 2006 page 631 of 680 REJ09B0145-0600...
Page 670: Figure C.1 (C) Port 1 Block Diagram (Pin P1
Appendix C I/O Port Block Diagrams Timer F module TMOFH (P1 TMOFL (P1 PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n= 2, 1 Figure C.1 (c) Port 1 Block Diagram (Pin P1 , P1 Rev.
Page 671: Figure C.1 (D) Port 1 Block Diagram (Pin P1
Appendix C I/O Port Block Diagrams Timer A module TMOW PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (d) Port 1 Block Diagram (Pin P1 Rev.
Page 672: Block Diagrams Of Port 2
Appendix C I/O Port Block Diagrams Block Diagrams of Port 2 PMR4 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR4: Port mode register 4 n = 7 to 3 Figure C.2 (a-1) Port 2 Block Diagram (Pins P2 to P2 , Not Including P2 in the F-ZTAT...
Page 673: Figure C.2 (A-2) Port 2 Block Diagram (Pin P2
Appendix C I/O Port Block Diagrams Reset signal (low level during reset) PMR4 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR4: Port mode register 4 Figure C.2 (a-2) Port 2 Block Diagram (Pin P2 in the F-ZTAT Version of the H8/38347 Group and H8/38447 Group) Rev.
Page 674: Figure C.2 (B) Port 2 Block Diagram (Pin P2
Appendix C I/O Port Block Diagrams SCI1 module PMR2 PMR4 PMR2 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (b) Port 2 Block Diagram (Pin P2 Rev.
Page 675: Figure C.2 (C) Port 2 Block Diagram (Pin P2
Appendix C I/O Port Block Diagrams PMR4 PMR2 PDR2 PCR2 SCI module PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (c) Port 2 Block Diagram (Pin P2 Rev.
Page 676: Figure C.2 (D) Port 2 Block Diagram (Pin P2
Appendix C I/O Port Block Diagrams SCI module EXCK PMR4 PMR2 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (d) Port 2 Block Diagram (Pin P2 Rev.
Page 677: Figure C.3 (A) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams Block Diagrams of Port 3 PUCR3 PMR3 PDR3 PCR3 AEC module AEVH(P3 AEVL(P3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n=7 to 6 Figure C.3 (a) Port 3 Block Diagram (Pin P3 to P3...
Page 678: Figure C.3 (B) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams PUCR3 SCINV1 SCI31 module TE31 TXD31 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 SCINV1: Bit 1 of serial port control register (SPCR) Figure C.3 (b) Port 3 Block Diagram (Pin P3 Rev.
Page 679: Figure C.3 (C) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams PUCR3 SCI31 module RE31 RXD31 PDR3 PCR3 SCINV0 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 SCINV0: Bit 0 of serial port control register (SPCR) Figure C.3 (c) Port 3 Block Diagram (Pin P3 Rev.
Page 680: Figure C.3 (D) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams PUCR3 SCI31 module SCKIE31 SCKOE31 SCKO31 SCKI31 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 Figure C.3 (d) Port 3 Block Diagram (Pin P3 Rev.
Page 681: Figure C.3 (E-1) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams RESO PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (e-1) Port 3 Block Diagram (Pin P3 , H8/3847R Group and H8/3847S Group) Rev.
Page 682: Figure C.3 (E-2) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (e-2) Port 3 Block Diagram (Pin P3 , H8/38347 Group and H8/38447 Group) Rev.
Page 683: Figure C.3 (F-1) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams PUCR3 PMR3 PDR3 PCR3 Timer C module PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (f-1) Port 3 Block Diagram (Pin P3 , H8/3847R Group and H8/3847S Group)) Rev.
Page 684: Figure C.3 (F-2) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams PMR2 PUCR3 PMR3 PDR3 PCR3 Timer C module Subclock oscillator Clock input PDR3: Port data register 3 PCR3: Port control register 3 PMR2: Port mode register 2 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (f-2) Port 3 Block Diagram (Pin P3 , H8/38347 Group and H8/38447 Group) Rev.
Page 685: Figure C.3 (G) Port 3 Block Diagram (Pin P3
Appendix C I/O Port Block Diagrams PWM module PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (g) Port 3 Block Diagram (Pin P3 Rev.
Page 686: Figure C.4 (A) Port 4 Block Diagram (Pin P4
Appendix C I/O Port Block Diagrams Block Diagrams of Port 4 PMR3 PMR3: Port mode register 3 Figure C.4 (a) Port 4 Block Diagram (Pin P4 Rev. 6.00 Aug 04, 2006 page 648 of 680 REJ09B0145-0600...
Page 687: Figure C.4 (B) Port 4 Block Diagram (Pin P4
Appendix C I/O Port Block Diagrams SCINV3 SCI32 module TE32 TXD32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 SCINV3: Bit 3 of serial port control register (SPCR) Figure C.4 (b) Port 4 Block Diagram (Pin P4 Rev.
Page 688: Figure C.4 (C) Port 4 Block Diagram (Pin P4
Appendix C I/O Port Block Diagrams SCI32 module RE32 RXD32 PDR4 PCR4 SCINV2 PDR4: Port data register 4 PCR4: Port control register 4 SCINV2: Bit 2 of serial port control register (SPCR) Figure C.4 (c) Port 4 Block Diagram (Pin P4 Rev.
Page 689: Figure C.4 (D) Port 4 Block Diagram (Pin P4
Appendix C I/O Port Block Diagrams SCI32 module SCKIE32 SCKOE32 SCKO32 SCKI32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (d) Port 4 Block Diagram (Pin P4 Rev. 6.00 Aug 04, 2006 page 651 of 680 REJ09B0145-0600...
Page 690: Figure C.5 Port 5 Block Diagram
Appendix C I/O Port Block Diagrams Block Diagram of Port 5 PUCR5 PMR5 PDR5 PCR5 PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Figure C.5 Port 5 Block Diagram Rev.
Page 691: Figure C.6 Port 6 Block Diagram
Appendix C I/O Port Block Diagrams Block Diagram of Port 6 PUCR6 PDR6 PCR6 PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.6 Port 6 Block Diagram Rev.
Page 692: Figure C.7 Port 7 Block Diagram
Appendix C I/O Port Block Diagrams Block Diagram of Port 7 PDR7 PCR7 PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.7 Port 7 Block Diagram Rev. 6.00 Aug 04, 2006 page 654 of 680 REJ09B0145-0600...
Page 693: Figure C.8 Port 8 Block Diagram
Appendix C I/O Port Block Diagrams Block Diagrams of Port 8 PDR8 PCR8 PDR8: Port data register 8 PCR8: Port control register 8 n= 7 to 0 Figure C.8 Port 8 Block Diagram Rev. 6.00 Aug 04, 2006 page 655 of 680 REJ09B0145-0600...
Page 694: Figure C.9 Port 9 Block Diagram
Appendix C I/O Port Block Diagrams Block Diagram of Port 9 PDR9 PCR9 PDR9: Port data register 9 PCR9: Port control register 9 n = 7 to 0 Figure C.9 Port 9 Block Diagram Rev. 6.00 Aug 04, 2006 page 656 of 680 REJ09B0145-0600...
Page 695: Figure C.10 Port A Block Diagram
Appendix C I/O Port Block Diagrams C.10 Block Diagram of Port A PDRA PCRA PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.10 Port A Block Diagram Rev. 6.00 Aug 04, 2006 page 657 of 680 REJ09B0145-0600...
Page 696: Figure C.11 Port B Block Diagram
Appendix C I/O Port Block Diagrams C.11 Block Diagram of Port B Internal data bus A/D module AMR3 to AMR0 n = 7 to 0 Figure C.11 Port B Block Diagram Rev. 6.00 Aug 04, 2006 page 658 of 680 REJ09B0145-0600...
Page 697: Figure C.12 Port C Block Diagram
Appendix C I/O Port Block Diagrams C.12 Block Diagram of Port C PC n A/D module AMR3 to 0 n = 3 to 0 Figure C.12 Port C Block Diagram Rev. 6.00 Aug 04, 2006 page 659 of 680 REJ09B0145-0600...
Page 698 Appendix D Port States in the Different Processing States Appendix D Port States in the Different Processing States Table D.1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active to P1 High- Retained Retained High- Retained Functions Functions impedance * impedance to P2...
Page 699 Appendix E List of Product Codes Appendix E List of Product Codes Table E.1 Product Code Lineup Product Type Product Code Mark Code Package (Package Code) H8/3847R H8/3842R Mask Regular HD6433842RH HD6433842R(***)H 100-pin QFP (FP-100B) Group products HD6433842RF HD6433842R(***)F 100-pin QFP (FP-100A) versions HD6433842RX HD6433842R(***)X 100-pin TQFP (TFP-100B)
Page 700 Appendix E List of Product Codes Product Type Product Code Mark Code Package (Package Code) H8/3847R H8/3845R Mask Regular HD6433845RH HD6433845R(***)H 100-pin QFP (FP-100B) Group products HD6433845RF HD6433845R(***)F 100-pin QFP (FP-100A) versions HD6433845RX HD6433845R(***)X 100-pin TQFP (TFP-100B) HD6433845RW HD6433845R(***)W 100-pin TQFP (TFP- 100G) ...
Page 701 Appendix E List of Product Codes Product Type Product Code Mark Code Package (Package Code) H8/3847S H8/3844S Mask Regular HD6433844SH HD6433844S(***)H 100-pin QFP (FP-100B) Group products HD6433844SX HD6433844S(***)X 100-pin TQFP (TFP-100B) versions HD6433844SW HD6433844S(***)W 100-pin TQFP (TFP- 100G)  HCD6433844S Wide- HD6433844SD HD6433844S(***)H 100-pin QFP (FP-100B)
Page 702 Appendix E List of Product Codes Product Type Product Code Mark Code Package (Package Code) H8/38347 H8/38342 Mask Regular HD64338342H 38342H 100-pin QFP (FP-100B) Group products HD64338342W 38342W 100-pin TQFP (TFP- versions 100G) 100-pin TQFP (TFP-100B) HD64338342X 38342X  HCD64338342 Wide- HD64338342HW 38342H 100-pin QFP (FP-100B)
Page 703 Appendix E List of Product Codes Product Type Product Code Mark Code Package (Package Code) H8/38347 H8/38345 Mask Regular HD64338345H 38345H 100-pin QFP (FP-100B) Group products HD64338345W 38345W 100-pin TQFP (TFP- versions 100G) 100-pin TQFP (TFP-100B) HD64338345X 38345X  HCD64338345 Mask HD64338345HW 38345H Wide-...
Page 704 Appendix E List of Product Codes Product Type Product Code Mark Code Package (Package Code) H8/38447 H8/38442 Mask Regular HD64338442H 38442H 100-pin QFP (FP-100B) Group products HD64338442W 38442W 100-pin TQFP (TFP- versions 100G) 100-pin TQFP (TFP-100B) HD64338442X 38442X  HCD64338442 Wide- HD64338442HW 38442H 100-pin QFP (FP-100B)
Page 705 Appendix E List of Product Codes Product Type Product Code Mark Code Package (Package Code) H8/38447 H8/38445 Mask Regular HD64338445H 38445H 100-pin QFP (FP-100B) Group products HD64338445W 38445W 100-pin TQFP (TFP- versions 100G) 100-pin TQFP (TFP-100B) HD64338445X 38445X  HCD64338445 Mask HD64338445HW 38445H Wide-...
Page 706: Appendix F Package Dimensions
Dimensional drawings of H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group packages FP-100A (only H8/3847R Group), FP-100B, TFP-100B and TFP-100G are shown in following figures F.1, F.2, F.3, and F.4, respectively. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x20-0.65...
Page 707: Figure F.2 Fp-100B Package Dimensions
Appendix F Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x14-0.50 PRQP0100KA-A FP-100B/FP-100BV 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Symbol 2.70 15.7 16.0 16.3 Terminal cross section 15.7...
Page 708: Figure F.3 Tfp-100B Package Dimensions
Appendix F Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP100-14x14-0.50 PTQP0100KA-A TFP-100B/TFP-100BV 0.5g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Symbol 1.00 15.8 16.0 16.2 Terminal cross section 15.8...
Page 709: Figure F.4 Tfp-100G Package Dimensions
Appendix F Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP100-12x12-0.40 PTQP0100LC-A TFP-100G/TFP-100GV 0.4g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Symbol 1.00 13.8 14.0 14.2 Terminal cross section 13.8...
Page 710: Appendix G Specifications Of Chip Form
Appendix G Specifications of Chip Form Appendix G Specifications of Chip Form The specifications of the chip form of the HCD6433847R, HCD6433846R, HCD6433845R, HCD6433844R, HCD6433843R, and HCD6433842R are shown in figure G.1. X-direction 6.10 ± 0.05 Y-direction 6.23 ± 0.05 0.28 ±...
Page 711: Figure G.3 Chip Sectional Figure
Appendix G Specifications of Chip Form The specifications of the chip form of the HCD64F38347 and HCD64F38447 are shown in figure G.3. X-direction 4.35 ± 0.05 Y-direction 4.83 ± 0.05 Pattern side 0.28 ± 0.22 Chip back Maximum plain Max 0.03 X-direction 4.35 ±...
Page 712: Appendix H Form Of Bonding Pads
Appendix H Form of Bonding Pads Appendix H Form of Bonding Pads The form of the bonding pads for the HCD6433847R, HCD6433846R, HCD6433845R, HCD6433844R, HCD6433843R, and HCD6433842R is shown in figure H.1. Bonding area Metal Layer 90 µm 5 to 8 µm Figure H.1 Bonding Pad Form Rev.
Page 713: Figure H.2 Bonding Pad Form
Appendix H Form of Bonding Pads The form of the bonding pads for the HCD6433847S, HCD6433846S, HCD6433845S, and HCD6433844S is shown in figure H.2. Bonding area Metal Layer 75 µm 2.5 µm Figure H.2 Bonding Pad Form Rev. 6.00 Aug 04, 2006 page 675 of 680 REJ09B0145-0600...
Page 714: Figure H.3 Bonding Pad Form
Appendix H Form of Bonding Pads The form of the bonding pads for the HCD64F38347, HCD64F38447, H8/38347 Group (Mask ROM version), and H8/38447 Group (Mask ROM version) is shown in figure H.3. Metal Layer Bonding area 5 µm 65 µm Figure H.3 Bonding Pad Form Rev.
Page 715: Appendix I Specifications Of Chip Tray
Appendix I Specifications of Chip Tray Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD6433847R, HCD6433846R, HCD6433845R, HCD6433844R, HCD6433843R, and HCD6433842R are shown in figure I.1. Chip orientation Chip 6.23 Type code 6.10 Chip-tray code name Manufactured by DAINIPPON INK AND CHEMICALS, INCORPORATED Code name: CT054...
Page 716: Figure I.2 Specifications Of Chip Tray
Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD6433847S, HCD6433846S, HCD6433845S, and HCD6433844S are shown in figure I.2. Chip orientation Type code Chip 3.45 Base type code 3.55 Chip-tray code name Manufactured by DAINIPPON INK AND CHEMICALS, INCORPORATED Code name: CT065 Characteristic engraving: TCT4040-060...
Page 717: Figure I.3 Specifications Of Chip Tray
Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD64F38347 and HCD64F38447 are shown in figure I.3. Chip orientation Type code 4.83 Chip 4.35 Chip-tray code name Code name: CT037 Characteristic engraving: 2CT049049-070 5.4 ± 0.1 4.9 ±...
Page 718: Figure I.4 Specifications Of Chip Tray
Appendix I Specifications of Chip Tray The specifications of the chip tray for the H8/38347 Group (Mask ROM version) and H8/38447 Group (Mask ROM version) are shown in figure I.4. Chip orientation Type code 3.77 Chip 3.55 Chip-tray code name Code name: CT127 Characteristic engraving: 2CT040040-063 5.5 ±...
Page 719 Publication Date: 1st Edition, September, 1999 Rev.6.00, August 04, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 720 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 721 H8/3847R Group, H8/3847S Group, H8/38347 Group, H8/38447 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0145-0600...

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H8/3847s series H8/38347 series H8/38447 series H8/3842r H8/3843r H8/3844r ... Show all

Renesas H8/3847R Series Hardware Manual

Section 1 Overview

Section 1 Overview

Section 2 CPU

Section 2 CPU

Section 2 CPU

Section 3 Exception Handling

Section 3 Exception Handling

Table 3.1 Exception Handling Types and Priorities

Section 3 Exception Handling

Section 4 Clock Pulse Generators

Section 4 Clock Pulse Generators

Section 5 Power-Down Modes

Section 5 Power-Down Modes

Section 5 Power-Down Modes

Section 6 ROM

Section 6 ROM

Section 6 ROM

Section 7 RAM

Section 7 RAM

Section 8 I/O Ports

Section 8 I/O Ports

Section 8 I/O Ports

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Summary of Contents for Renesas H8/3847R Series