Figure 16.9 Slave Transmit Mode Operation Timing (1) - Renesas HD6417641 Hardware Manual

2
Section 16 I C Bus Interface 2 (IIC2)
5. Clear TDRE.
Slave receive mode
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
TDRE
TEND
TRS
ICDRT
ICDRS
ICDRR
User
[2] Write data to ICDRT (data 1)
processing

Figure 16.9 Slave Transmit Mode Operation Timing (1)

Rev. 4.00 Sep. 14, 2005 Page 494 of 982
REJ09B0023-0400
Slave transmit mode
9 1 2
Bit 7 Bit 6
A
Data 1
Data 1
[2] Write data to ICDRT (data 2)
3 4 5 6
Bit 5 Bit 4 Bit 3 Bit 2
7 8 9 1
A
Bit 1 Bit 0 Bit 7
Data 2 Data 3
Data 2
[2] Write data to ICDRT (data 3)