NXP Semiconductors MC68HC16Z3 Manuals

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NXP Semiconductors MC68HC16Z3 User Manual

NXP Semiconductors MC68HC16Z3 User Manual (501 pages)

M68HC16Z Series

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 5 MB

Table of Contents

Table of Contents
3
Nomenclature

29
- Symbols and Operators
  29
- CPU16 Register Mnemonics
  30
- Register Mnemonics
  31
- Conventions
  34
Section 3

35
Overview

35
Central Processor Unit

61
- General
  61
- Register Model
  61
- Accumulators
  63
- Index Registers
  63
- Stack Pointer
  63
- Program Counter
  63
- Condition Code Register
  64
- Address Extension Register and Address Extension Fields
  65
- Multiply and Accumulate Registers
  65
- Memory Management
  65
- Address Extension
  66
- Extension Fields
  66
- Data Types
  66
- Memory Organization
  67
- Addressing Modes
  68
- Immediate Addressing Modes
  69
- Extended Addressing Modes
  70
- Indexed Addressing Modes
  70
- Inherent Addressing Mode
  70
- Accumulator Offset Addressing Mode
  70
- Relative Addressing Modes
  70
- Post-Modified Index Addressing Mode
  70
- Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode
  71
- Instruction Set
  71
- Instruction Set Summary
  71
- Comparison of CPU16 and M68HC11 CPU Instruction Sets
  91
- Instruction Format
  93
- Execution Model
  94
- Microsequencer
  95
- Instruction Pipeline
  95
- Execution Unit
  95
- Execution Process
  96
- Changes in Program Flow
  96
- Instruction Timing
  96
- Exceptions
  97
- Exception Vectors
  97
- Exception Stack Frame
  98
- Exception Processing Sequence
  99
- Types of Exceptions
  99
- Asynchronous Exceptions
  99
- Synchronous Exceptions
  99
  - Interrupt Exception Processing
    99
- Multiple Exceptions
  100
- RTI Instruction
  100
- Development Support
  100
- Deterministic Opcode Tracking
  100
- IPIPE0/IPIPE1 Multiplexing
  101
- Combining Opcode Tracking with Other Capabilities
  101
- Breakpoints
  101
- Opcode Tracking and Breakpoints
  102
  - Background Debug Mode
    102
    
    Enabling BDM
    102
    
    BDM Sources
    102
    
    Entering BDM
    102
    
    BDM Commands
    103
    
    Returning from BDM
    103
    
    BDM Serial Interface
    104
- Recommended BDM Connection
  105
- Digital Signal Processing
  105
  - System Integration Module
    107
- General
  107
- System Configuration
  108
  - Module Mapping
    108
  - Interrupt Arbitration
    109
  - Show Internal Cycles
    109
  - Register Access
    109
  - Freeze Operation
    109
- System Clock
  110
  - Clock Sources
    111
  - Clock Synthesizer Operation
    112
  - External Bus Clock
    127
  - Low-Power Operation
    127
- System Protection
  130
  - Reset Status
    130
  - Bus Monitor
    130
  - Halt Monitor
    131
  - Spurious Interrupt Monitor
    131
  - Software Watchdog
    131
  - Periodic Interrupt Timer
    133
  - Interrupt Priority and Vectoring
    134
  - Low-Power STOP Operation
    135
- External Bus Interface
  135
  - Bus Control Signals
    137
    
    Address Bus
    137
    
    Address Strobe
    137
    
    Data Bus
    137
    
    Data Strobe
    137
    
    Read/Write Signal
    138
    
    Size Signals
    138
    
    Function Codes
    138
    
    Data Size Acknowledge Signals
    138
    
    Bus Error Signal
    139
    
    Halt Signal
    139
    
    Autovector Signal
    139
  - Dynamic Bus Sizing
    139
  - Operand Alignment
    141
  - Misaligned Operands
    141
  - Operand Transfer Cases
    141
- Bus Operation
  142
  - Synchronization to CLKOUT
    142
  - Regular Bus Cycle
    142
    
    Read Cycle
    143
  - Fast Termination Cycles
    143
  - CPU Space Cycles
    146
    
    Breakpoint Acknowledge Cycle
    147
    
    LPSTOP Broadcast Cycle
    148
  - Bus Exception Control Cycles
    149
    
    Bus Errors
    150
    
    Double Bus Faults
    151
    
    Halt Operation
    151
  - External Bus Arbitration
    152
    
    Show Cycles
    153
- Reset
  154
  - Reset Exception Processing
    154
  - Reset Control Logic
    154
  - Reset Mode Selection
    155
    
    Data Bus Mode Selection
    156
    
    Clock Mode Selection
    158
    
    Breakpoint Mode Selection
    158
  - MCU Module Pin Function During Reset
    158
  - Pin State During Reset
    159
    
    Reset States of SIM Pins
    160
    
    Reset States of Pins Assigned to Other MCU Modules
    160
  - Reset Timing
    161
  - Power-On Reset
    161
  - Use of the Three-State Control Pin
    162
  - Reset Processing Summary
    163
  - Reset Status Register
    163
  - Interrupt Acknowledge and Arbitration
    165
  - Interrupt Processing Summary
    166
  - Interrupt Acknowledge Bus Cycles
    167
  - Chip-Select Registers
    169
    
    Chip-Select Pin Assignment Registers
    170
    
    Chip-Select Base Address Registers
    171
    
    Chip-Select Option Registers
    171
    
    Chip-Select Option Registers
    172
    
    PORTC Data Register
    173
  - Chip-Select Operation
    173
  - Using Chip-Select Signals for Interrupt Acknowledge
    174
  - Chip-Select Reset Operation
    175
- Parallel Input/Output Ports
  176
  - Pin Assignment Registers
    176
  - Data Direction Registers
    176
  - Data Registers
    177
- Factory Test
  177
  - Standby Ram Module
    179
- SRAM Register Block
  179
- SRAM Array Address Mapping
  180
- SRAM Array Address Space Type
  180
- Normal Access
  180
- Standby and Low-Power Stop Operation
  180
- Reset
  181
  - Masked Rom Module
    183
- MRM Register Block
  183
- MRM Array Address Mapping
  183
- MRM Array Address Space Type
  184
- Normal Access
  184
- Low-Power Stop Mode Operation
  185
- ROM Signature
  185
- Reset
  185
- General
  187
- External Connections
  187
  - Analog Input Pins
    188
  - Analog Reference Pins
    189
  - Analog Supply Pins
    189
- Programmer's Model
  189
- ADC Bus Interface Unit
  189
- Special Operating Modes
  189
  - Low-Power Stop Mode
    189
  - Freeze Mode
    190
- Analog Subsystem
  190
  - Multiplexer
    190
  - Sample Capacitor and Buffer Amplifier
    191
  - RC DAC Array
    191
  - Comparator
    192
- Digital Control Subsystem
  192
  - Control/Status Registers
    192
  - Clock and Prescaler Control
    192
  - Sample Time
    193
  - Resolution
    193
  - Conversion Control Logic
    193
    
    Conversion Parameters
    194
    
    Conversion Modes
    194
  - Conversion Timing
    198
  - Successive Approximation Register
    199
  - Result Registers
    199
- Pin Considerations
  200
  - Analog Reference Pins
    200
  - Analog Power Pins
    200
  - Analog Supply Filtering and Grounding
    202
  - Accommodating Positive/Negative Stress Conditions
    204
  - Analog Input Considerations
    205
  - Analog Input Pins
    207
    
    Settling Time for the External Circuit
    208
    
    Error Resulting from Leakage
    209
    
    Queued Serial Module
    211
- General
  211
- QSM Registers and Address Map
  212
  - QSM Global Registers
    212
    
    Low-Power Stop Mode Operation
    212
    
    Freeze Operation
    213
    
    QSM Interrupts
    213
  - QSM Pin Control Registers
    214
- Queued Serial Peripheral Interface
  215
  - QSPI Registers
    216
    
    Control Registers
    216
    
    Status Register
    217
  - Qspi Ram
    217
    
    Receive RAM
    217
    
    Transmit RAM
    217
    
    Command RAM
    218
  - QSPI Pins
    218
  - QSPI Operation
    218
  - QSPI Operating Modes
    219
    
    Master Mode
    226
    
    Master Wrap-Around Mode
    229
    
    Slave Mode
    230
    
    Slave Wrap-Around Mode
    231
  - Peripheral Chip Selects
    231
- Serial Communication Interface
  231
  - SCI Registers
    234
    
    Control Registers
    234
    
    Status Register
    234
    
    Data Register
    234
  - SCI Pins
    235
  - SCI Operation
    235
    
    Definition of Terms
    235
    
    Serial Formats
    235
    
    Baud Clock
    236
    
    Parity Checking
    236
    
    Transmitter Operation
    237
    
    Receiver Operation
    238
    
    Idle-Line Detection
    239
    
    Receiver Wake-Up
    239
    
    Internal Loop Mode
    240
- General
  241
- MCCI Registers and Address Map
  242
  - MCCI Global Registers
    242
    
    Low-Power Stop Mode
    242
    
    Privilege Levels
    243
    
    MCCI Interrupts
    243
  - Pin Control and General-Purpose I/O
    244
- Serial Peripheral Interface (SPI)
  244
  - SPI Registers
    246
    
    SPI Control Register (SPCR)
    246
    
    SPI Status Register (SPSR)
    246
    
    SPI Data Register (SPDR)
    246
  - SPI Pins
    246
  - SPI Operating Modes
    247
    
    Master Mode
    247
    
    Slave Mode
    248
  - SPI Clock Phase and Polarity Controls
    248
    
    CPHA = 0 Transfer Format
    249
    
    CPHA = 1 Transfer Format
    250
  - SPI Serial Clock Baud Rate
    251
  - Wired-OR Open-Drain Outputs
    251
  - Transfer Size and Direction
    251
  - Write Collision
    252
  - Mode Fault
    252
- Serial Communication Interface (SCI)
  253
  - SCI Registers
    253
    
    SCI Control Registers
    253
    
    SCI Status Register
    256
    
    SCI Data Register
    256
  - SCI Pins
    256
  - Receive Data Pins (RXDA, RXDB)
    257
  - Transmit Data Pins (TXDA, TXDB)
    257
  - SCI Operation
    257
    
    Definition of Terms
    257
    
    Serial Formats
    258
    
    Baud Clock
    258
    
    Parity Checking
    259
    
    Transmitter Operation
    259
    
    Receiver Operation
    260
    
    Idle-Line Detection
    261
    
    Receiver Wake-Up
    262
    
    Internal Loop
    262
- MCCI Initialization
  263
  - General-Purpose Timer
    265
- General
  265
- GPT Registers and Address Map
  266
- Special Modes of Operation
  267
  - Low-Power Stop Mode
    267
  - Freeze Mode
    267
  - Single-Step Mode
    268
  - Test Mode
    268
- Polled and Interrupt-Driven Operation
  268
  - Polled Operation
    268
- Interrupts
  269
  - GPT Interrupts
    269
- Pin Descriptions
  271
  - Input Capture Pins
    271
  - Input Capture/Output Compare Pin
    271
  - Output Compare Pins
    271
  - Pulse Accumulator Input Pin
    271
  - Pulse-Width Modulation
    272
  - Auxiliary Timer Clock Input
    272
- General-Purpose I/O
  272
- Prescaler
  272
- Capture/Compare Unit
  274
  - Timer Counter
    274
  - Input Capture Functions
    274
  - Output Compare Functions
    277
    
    Output Compare 1
    278
    
    Forced Output Compare
    278
- Input Capture 4/Output Compare 5
  278
- Pulse Accumulator
  278
- Pulse-Width Modulation Unit
  280
  - PWM Counter
    282
  - PWM Function
    282
    
    B.1 Obtaining Updated M68HC16 Z-Series MCU Mechanical Information
    364
    
    C.1 M68MMDS1632 Modular Development System
    373
    
    C.2 M68MEVB1632 Modular Evaluation Board
    374
    
    D.1 Central Processing Unit
    375
    
    D.1.1 Condition Code Register
    377
    
    D.2 System Integration Module
    378
    
    D.2.1 SIM Module Configuration Register
    380
    
    D.2.2 System Integration Test Register
    381
    
    D.2.4 Reset Status Register
    382
    
    D.2.5 System Integration Test Register E
    383
    
    D.2.8 Port E Pin Assignment Register
    384
    
    D.2.10 Port F Data Direction Register
    385
    
    D.2.12 System Protection Control Register
    386
    
    D.2.13 Periodic Interrupt Control Register
    387
    
    D.2.14 Periodic Interrupt Timer Register
    388
    
    D.2.15 Software Watchdog Service Register
    389
    
    D.2.18 Chip-Select Base Address Register Boot
    391
    
    D.2.20 Chip-Select Option Register Boot
    392
    
    D.2.22 Master Shift Registers
    396
    
    D.3 Standby RAM Module
    397
    
    D.3.2 RAM Test Register
    398
    
    D.4 Masked ROM Module
    399
    
    D.4.2 ROM Array Base Address Registers
    401
    
    D.4.4 ROM Bootstrap Words
    402
    
    D.5 Analog-To-Digital Converter Module
    403
    
    D.5.1 ADC Module Configuration Register
    404
    
    D.5.4 ADC Control Register 0
    405
    
    D.5.5 ADC Control Register 1
    406
    
    D.5.6 ADC Status Register
    410
    
    D.6 Queued Serial Module
    412
    
    D.6.2 QSM Test Register
    413
    
    D.6.4 SCI Control Register
    414
    
    D.6.5 SCI Control Register 1
    415
    
    D.6.6 SCI Status Register
    417
    
    D.6.7 SCI Data Register
    418
    
    D.6.9 Port QS Pin Assignment Register/Data Direction Register
    419
    
    D.6.10 QSPI Control Register 0
    420
    
    D.6.11 QSPI Control Register 1
    422
    
    D.6.12 QSPI Control Register 2
    423
    
    D.6.13 QSPI Control Register 3
    424
    
    D.6.14 Receive Data RAM
    425
    
    D.6.15 Transmit Data RAM
    426
    
    D.7 Multichannel Communication Interface Module
    428
    
    D.7.2 MCCI Test Register
    429
    
    D.7.4 MCCI Interrupt Vector Register
    430
    
    D.7.6 MCCI Pin Assignment Register
    431
    
    D.7.7 MCCI Data Direction Register
    432
    
    D.7.8 MCCI Port Data Registers
    433
    
    D.7.11 SCI Status Register
    436
    
    D.7.12 SCI Data Register
    437
    
    D.7.13 SPI Control Register
    438
    
    D.7.14 SPI Status Register
    439
    
    D.7.15 SPI Data Register
    440
    
    D.8 General-Purpose Timer
    441
    
    D.8.2 GPT Test Register
    442
    
    D.8.4 Port GP Data Direction Register/Data Register
    443
    
    D.8.6 Timer Counter Register
    444
    
    D.8.8 Input Capture Registers 1–3
    445
    
    D.8.10 Input Capture 4/Output Compare 5 Register
    446
    
    D.8.13 Timer Interrupt Flag Registers 1 and 2
    448
    
    D.8.15 PWM Registers A/B
    450
    
    D.8.18 GPT Prescaler
    451
    
    E.1 Initialization Programs
    453
    
    E.1.1 Equates.asm
    454
    
    E.1.2 Org00000.Asm
    458
    
    E.1.4 Initsys.asm
    463
    
    E.1.6 Initsci.asm
    464
    
    E.2.1 SIM Programming Examples
    465
    
    E.2.1.2 Example 2 - Using Chip-Selects
    466
    
    E.2.1.3 Example 3 - Changing Clock Frequencies
    468
    
    E.2.1.4 Example 4 - Software Watchdog, Periodic Interrupt and Autovector Demo
    470
    
    E.2.2 CPU16 Programming Example
    475
    
    E.2.3 QSM/SCI Programming Example
    476
    
    E.2.4 GPT Programming Example
    477

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