Core Privilege Levels; Nested Vectored Interrupt Controller (Nvic) Configuration; Interrupt Priority Levels; Non-Maskable Interrupt - NXP Semiconductors freescale KV4 Series Reference Manual

3.1.4 Core privilege levels

The ARM documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term...
Privileged
Unprivileged or user
3.2 Nested Vectored Interrupt Controller (NVIC)
Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at arm.com.

3.2.1 Interrupt priority levels

This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source
in the IPR registers contains 4 bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25
R 0 0 0
IRQ3
W

3.2.2 Non-maskable interrupt

The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to
generate the non-maskable interrupt request.
Freescale Semiconductor, Inc.
Nested Vectored
ARM PPB
Interrupt Controller
Cortex-M4
core
(NVIC)
Figure 3-2. NVIC configuration
24 23 22 21 20 19 18 17
0 0 0 0
IRQ2
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
it also means this term...
Supervisor
User
Interrupts
Module
Module
Module
16 15 14 13 12 11 10 9
0 0 0 0
IRQ1
Chapter 3 Core overview
8 7 6 5 4 3 2 1
0 0 0 0
IRQ0
0
0
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