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Nested vectored interrupt controller (NVIC)
3.1.4 Core privilege levels
The core on this device is implemented with both privileged and unprivileged levels. The
ARM documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term...
Privileged
Unprivileged or user
3.2
Nested vectored interrupt controller (NVIC)
3.2.1 Interrupt priority levels
This device supports four priority levels for interrupts. Therefore, in the NVIC, each
source in the IPR registers contains two bits. For example, IPR0 is shown below:
31
30
29
28
27
26
25
R
0
0
0
0
IRQ3
W
3.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to
generate the non-maskable interrupt request.
3.2.3 Interrupt channel assignments
The interrupt vector assignments are defined in the following table.
• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
50
24
23
22
21
20
19
18
0
0
0
0
0
0
IRQ2
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
it also means this term...
Supervisor
User
17
16
15
14
13
12
11
10
0
0
0
0
0
0
IRQ1
9
8
7
6
5
4
3
2
0
0
0
0
0
0
IRQ0
Freescale Semiconductor, Inc.
1
0
0
0
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