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NXP Semiconductors
Bit
Symbol
0
ee_prog_dat_completed_int_SE
T_STATUS
4. Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M0. The tight coupling to the CPU allows for a
low interrupt latency and efficient processing of late arriving interrupts. The NVIC controls
system exceptions and peripheral interrupts. Its control registers are accessible as
memory-mapped devices.
4.1 NVIC features
•
•
•
•
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4.2 Interrupt sources
The following table lists the interrupt sources available in the PN7462 family
microcontroller
Table 28. External interrupt sources
EIRQ# Source
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UM10858
User manual
COMPANY PUBLIC
Access
W
Controls system exceptions and peripheral interrupts
Supports 32 vectored interrupts
Four interrupt priority levels, with hardware priority level masking
Non-mask able interrupt (NMI) connected to the watchdog interrupt.
Software interrupt generation
Timer 0/1/2/3
-
CLIF
EECTRL
-
-
Host IF
Contact IF
-
PMU/
TXLDO
SPIMaster
I2CMaster
PCR
PCR
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Value
Description
0
EEPROM programming completed
interrupt set status command
Description
general-purpose timer 0/1/2/3 interrupt
Reserved
contactless interface module interrupt
EEPROM controller
Reserved
Reserved
TX or RX buffer from I2C, SPI, HSU, or USB module
ISO7816 contact module interrupt
Reserved
power management unit (temperature sensor, TXLDO
overcurrent detection, overload, VBUS level)
TX or RX buffer from SPI master module
TX or RX buffer from I2C master module
high temperature from temperature sensor 0 and 1,
interrupt to CPU from PCR to indicate wakeup from suspend
mode, out of standby, out of suspend, event on GPIO's
configured as inputs.
interrupt common GPIO 1 to 12
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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