Pwm Generator Loading - NXP Semiconductors freescale KV4 Series Reference Manual

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Figure 37-249. Manual Fault Clearing (FCTRL[FSAFE]=0)

Figure 37-250. Manual Fault Clearing (FCTRL[FSAFE]=1)

Fault protection also applies during software output control

when the SEL23 and SEL45 fields are set to select OUT23 and

OUT45 bits or PWM_EXTA and PWM_EXTB. Fault clearing

still occurs at half PWM cycle boundaries while the PWM

generator is engaged, MCTRL[RUN] equals one. But the

OUTx bits can control the PWM pins while the PWM generator

is off, MCTRL[RUN] equals zero. Thus, fault clearing occurs

at IPBus cycles while the PWM generator is off and at the start

of PWM cycles when the generator is engaged.

37.5.2.12.4 Fault Testing

FTST[FTEST] is used to simulate a fault condition on each of the fault inputs within that

fault channel.

37.5.3 PWM Generator Loading

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)