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NXP Semiconductors
7. Clock generator
The PN7462 family uses following clock sources:
• External 27.12 MHz crystal oscillator
• Internal 20 MHz HFO (High Frequency Oscillator)
• Internal 380 kHz LFO (Low Frequency Oscillator)
• Internal 48 MHz USB PLL (Phase Lock Loop)
• Internal CLIF PLL (Phase Lock Loop)
In addition to the clock sources, the clock generator comprises a digital control unit,
which controls and monitors the signals coming from the clocks and integrated PLL. The
registers are accessed using an APB register interface.
7.1 Oscillators
The PN7462 family includes three independent oscillators. Each oscillator can be used
for more than one purposes. Upon reset, the PN7462 family will operate from the Internal
HFO until it is switched to a different clock source. This allows systems to operate
without any external crystal and the boot loader code to operate at a known frequency.
UM10858
User manual
COMPANY PUBLIC
Fig 18. Clock generator block diagram
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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