Output Compare Capabilities - NXP Semiconductors freescale KV4 Series Reference Manual

Functional Description
counter initialization, they can be used to modulate the duty cycle of the Local Sync
signal, effectively turning it into an auxiliary PWM signal (PWM_X) assuming that the
PWM_X pin is not being used for another function such as input capture or deadtime
distortion correction. Including the Local Sync signal, each submodule is capable of
generating three PWM signals where software has complete control over each edge of
each of the signals.
If the comparators and edge value registers are not required for PWM generation, they
can also be used for other functions such as output compares, generating output triggers,
or generating interrupts at timed intervals.
The 16-bit comparators shown in
the flip-flop are asserted, then the flop output goes to 0.

37.5.2.5 Output Compare Capabilities

By using the VALx registers in conjunction with the submodule timer and 16 bit
comparators, buffered output compare functionality can be achieved with no additional
hardware required. Specifically, the following output compare functions are possible:
• An output compare sets the output high
• An output compare sets the output low
• An output compare generates an interrupt
• An output compare generates an output trigger
In PWM generation, an output compare is initiated by programming a VALx register for
a timer compare, which in turn causes the output of the D flip-flop to either set or reset.
For example, if an output compare is desired on the PWM_A signal that sets it high,
VAL2 would be programmed with the counter value where the output compare should
take place. However, to prevent the D flip-flop from being reset again after the compare
has occurred, the VAL3 register must be programmed to a value outside of the modulus
range of the counter. Therefore, a compare that would result in resetting the D flip-flop
output would never occur. Conversely, if an output compare is desired on the PWM_A
signal that sets it low, the VAL3 register is programmed with the appropriate count value
and the VAL2 register is programmed with a value outside the counter modulus range.
Regardless of whether a high compare or low compare is programmed, an interrupt or
output trigger can be generated when the compare event occurs.
840
Figure 37-237 In addition, if both the set and reset of
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
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