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channel (n) input
timer module clock
The CHnF bit is set on the third rising edge of the counter clock after a valid edge occurs
on the channel input.
29.5.5 Output Compare Mode
The output compare mode is selected when (CPWMS = 0), and (MSnB:MSnA = X:1).
In output compare mode, the TPM can generate timed pulses with programmable
position, polarity, duration, and frequency. When the counter matches the value in the
CnV register of an output compare channel, the channel (n) output can be set, cleared or
toggled if MSnB is clear. If MSnB is set then the channel (n) output is pulsed high or low
for as long as the counter matches the value in the CnV register.
When a channel is initially configured to output compare mode, the channel output
updates with its negated value (logic 0 for set/toggle/pulse high and logic one for clear/
pulse low).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (TPM counter = CnV).
Freescale Semiconductor, Inc.
synchronizer
D
Q
D
Q
CLK
CLK
Figure 29-5. Input capture mode
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 29 Timer/PWM Module (TPM)
was rising
edge selected?
CHnIE
0
0
CHnF
rising edge
1
edge
detector
1
falling edge
0
0
was falling
edge selected?
channel (n) interrupt
CnV
timer module counter
479
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