Altera cyclone V Technical Reference page 2061

17-846
Status
Bit
19:17
rs
16
nis
15
ais
Altera Corporation
Name
This field indicates the Receive DMA FSM state. This
field does not generate an interrupt.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Normal Interrupt Summary bit value is the logical OR
of the following when the corresponding interrupt
bits are enabled in Register 7 (Interrupt Enable
Register): * Register 5[0]: Transmit Interrupt *
Register 5[2]: Transmit Buffer Unavailable * Register
5[6]: Receive Interrupt * Register 5[14]: Early Receive
Interrupt Only unmasked bits (interrupts for which
interrupt enable is set in Register 7) affect the Normal
Interrupt Summary bit. This is a sticky bit and must
be cleared (by writing 1 to this bit) each time a
corresponding bit, which causes NIS to be set, is
cleared.
Abnormal Interrupt Summary bit value is the logical
OR of the following when the corresponding
interrupt bits are enabled in Register 7 (Interrupt
Enable Register): * Register 5[1]: Transmit Process
Stopped * Register 5[3]: Transmit Jabber Timeout *
Register 5[4]: Receive FIFO Overflow * Register 5[5]:
Transmit Underflow * Register 5[7]: Receive Buffer
Unavailable * Register 5[8]: Receive Process Stopped *
Register 5[9]: Receive Watchdog Timeout * Register
5[10]: Early Transmit Interrupt * Register 5[13]: Fatal
Bus Error Only unmasked bits affect the Abnormal
Interrupt Summary bit. This is a sticky bit and must
be cleared each time a corresponding bit, which
causes AIS to be set, is cleared.
Description
Description
Stopped Reset or Stop Receive Command
issued
Running: Fetching Receive Transfer
Descriptor
Reserved for future use
Running: Waiting for receive packet
Suspended: Receive Descriptor Unavailable
Running: Closing Receive Descriptor
TIME_STAMP write state
Transferring rcv packet data from receive
buffer to host memory
2016.10.28
Access Reset
RO 0x0
RW 0x0
RW 0x0
Ethernet Media Access Controller
Send Feedback
cv_5v4