Altera cyclone V Technical Reference page 2056

Hard processor system

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Receive_Poll_Demand Fields

Receive_Descriptor_List_Address

The Receive Descriptor List Address register points to the start of the Receive Descriptor List. The

descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned

(for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by

making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped.

When stopped, this register must be written to before the receive Start command is given. You can write to

this register only when Rx DMA has stopped, that is, Bit 1 (SR) is set to zero in Register 6 (Operation

Mode Register). When stopped, this register can be written with a new descriptor list address. When you

set the SR bit to 1, the DMA takes the newly programmed descriptor base address. If this register is not

changed when the SR bit is set to 0, then the DMA takes the descriptor address where it was stopped

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Ethernet Media Access Controller

Send Feedback

When these bits are written with any value, the DMA

reads the current descriptor pointed to by Register 19

(Current Host Receive Descriptor Register). If that

descriptor is not available (owned by the Host), the

reception returns to the Suspended state and the Bit 7

(RU) of Register 5 (Status Register) is not asserted. If

the descriptor is available, the Rx DMA returns to the

active state.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

rdesla_32bit

Base Address

rdesla_32bit

Receive_Descriptor_List_Address

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