Altera cyclone V Technical Reference page 2059

Hard processor system

Hide thumbs Also See for cyclone V:

Table of Contents

Status Fields

Altera Corporation

This bit indicates an interrupt event in the LPI logic of

the EMAC. To reset this bit to 1'b0, the software must

read the corresponding registers in the EMAC to get

the exact cause of the interrupt and clear its source.

When this bit is high, the interrupt signal from the

MAC (sbd_intr_o) is high.

This bit indicates an interrupt event in the Timestamp

Generator block of EMAC. The software must read

the corresponding registers in the EMAC to get the

exact cause of interrupt and clear its source to reset

this bit to 1'b0. When this bit is high, the interrupt

signal from the EMAC subsystem (sbd_intr_o) is

This bit reflects an interrupt event in the MMC block

of the EMAC. The software must read the

corresponding registers in the EMAC to get the exact

cause of interrupt and clear the source of interrupt to

make this bit as 1'b0. The interrupt signal from the

EMAC subsystem (sbd_intr_o) is high when this bit

No Interrupt

GMAC LPI Interrupt

No Interrupt

Timestamp Trigger Interrupt

No Interrupt

GMAC MMC Interrupt

Ethernet Media Access Controller

Send Feedback

Show Quick Links

Table of Contents