Altera cyclone V Technical Reference page 2062

cv_5v4
2016.10.28
Bit
14
eri
13
fbi
10
eti
9
rwt
8
rps
7
ru
6
ri
5
unf
4
ovf
Ethernet Media Access Controller
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Name
This bit indicates that the DMA had filled the first
data buffer of the packet. Bit 6 (RI) of this register
automatically clears this bit.
This bit indicates that a bus error occurred, as
described in Bits[25:23]. When this bit is set, the
corresponding DMA engine disables all of its bus
accesses.
This bit indicates that the frame to be transmitted is
fully transferred to the MTL Transmit FIFO.
This bit is asserted when a frame with length greater
than 2,048 bytes is received (10, 240 when Jumbo
Frame mode is enabled).
This bit is asserted when the Receive Process enters
the Stopped state.
This bit indicates that the host owns the Next
Descriptor in the Receive List and the DMA cannot
acquire it. The Receive Process is suspended. To
resume processing Receive descriptors, the host
should change the ownership of the descriptor and
issue a Receive Poll Demand command. If no Receive
Poll Demand is issued, the Receive Process resumes
when the next recognized incoming frame is received.
This bit is set only when the previous Receive
Descriptor is owned by the DMA.
This bit indicates that the frame reception is complete.
When reception is complete, the Bit 31 of RDES1
(Disable Interrupt on Completion) is reset in the last
Descriptor, and the specific frame status information
is updated in the descriptor. The reception remains in
the Running state.
This bit indicates that the Transmit Buffer had an
Underflow during frame transmission. Transmission
is suspended and an Underflow Error TDES0[1] is
set.
This bit indicates that the Receive Buffer had an
Overflow during frame reception. If the partial frame
is transferred to the application, the overflow status is
set in RDES0[11].
Description
17-847
Status
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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