Altera cyclone V Technical Reference page 2053

17-838
Bus_Mode
Bit
13:8
pbl
7
atds
6:2
dsl
Altera Corporation
Name
These bits indicate the maximum number of beats to
be transferred in one DMA transaction. This is the
maximum value that is used in a single block Read or
Write. The DMA always attempts to burst as specified
in PBL each time it starts a Burst transfer on the host
bus. PBL can be programmed with permissible values
of 1, 2, 4, 8, 16, and 32. Any other value results in
undefined behavior. When USP is set high, this PBL
value is applicable only for Tx DMA transactions. If
the number of beats to be transferred is more than 32,
then perform the following steps: 1. Set the 8xPBL
mode. 2. Set the PBL. For example, if the maximum
number of beats to be transferred is 64, then first set
8xPBL to 1 and then set PBL to 8. The PBL values
have the following limitation: The maximum number
of possible beats (PBL) is limited by the size of the Tx
FIFO and Rx FIFO in the MTL layer and the data bus
width on the DMA. The FIFO has a constraint that
the maximum beat supported is half the depth of the
FIFO, except when specified.
When set, the size of the alternate (enhanced)
descriptor increases to 32 bytes (8 DWORDS). When
clear, the alternate (enhanced) descriptor size is 16
bytes (4 DWORDS).
Value
0x0
0x1
This bit specifies the number of Word, Dword, or
Lword (depending on the 32-bit, 64-bit, or 128-bit
bus) to skip between two unchained descriptors. The
address skipping starts from the end of current
descriptor to the start of next descriptor. When the
DSL value is equal to zero, then the descriptor table is
taken as contiguous by the DMA in Ring mode.
Description
Description
Descriptor size is 16 bytes (4 DWORDS)
Descriptor size is 32 bytes (8 DWORDS)
2016.10.28
Access Reset
RW 0x1
RW 0x0
RW 0x0
Ethernet Media Access Controller
Send Feedback
cv_5v4